DFT boot camp, Part 1: Scan test

My colleagues from Mentor Graphics, Ron Press, Martin Keim, and I often discuss various aspects of digital IC test. If you don't design and test digital ICs, then you may wonder what we have been talking about. If you're a board or systems designer but not an IC designer, you may also wonder how digital ICs are designed and tested before they reach you. As a result, we've opened design-for-test (DFT) boot camp. Over the next several articles, we will cover the basics of DFT and familiarize you with the concepts that may be foreign to you.

What is IC test?
Digital ICs are tested after manufacturing by placing them into automated test equipment (ATE) and applying combinations of logic values (so-called test patterns) to the inputs and measuring the response on the outputs. In the early days, engineers would create test patterns by simulating the operational modes of the device under test (DUT). As logic devices become more complex, this approach became untenable—it simply took too much time and effort to create and validate the tests, it was too hard to determine test coverage, and the tests took too long to run. Manufacturers need an automated way to create fast and efficient test patterns, while maintaining high test quality and circuit coverage.

Scan Test: Today's Standard for ICs
The industry moved to a DFT approach, meaning that the device itself was modified during design to make it easier to test. The approach that ended up dominating IC test is called structural, or "scan," test because it involves scanning test patterns into internal circuits within the DUT. To enable this, the design's flip-flops are modified to let them function as stimulus and observation points, or "scan cells" during test.

In effect, scan cells break the design into small segments of combinational logic that can be easily tested (figure). For a design with a million flops, introducing scan cells is like adding a million control and observation points. Segmenting the logic in this manner makes it feasible to automatically generate test patterns that can exercise the logic between the flops. The test software doesn't need to understand the function of the logic—it just tries to exercise the logic segments observed by a scan cell. Because scan test replaces flip flops that are already in the design with scan cells, the impact of the test circuitry is relatively small, typically adding about only 1% to 5% to the total gate count.