Enabling robust detection of scan coverage

Digital integrated circuits generally utilise asynchronous set/resets to set the value of memory elements (flip-flops) without depending on any clock pulses. This logic, however, requires special handling during scan based testing of the device. Also, the logic associated with asynchronous set/reset may constitute 2-4% of the total faults in a design. With growing focus on high test-coverage and zero DPPM, especially for critical applications like automotive and medical devices, it is important to thoroughly test such faults to ensure overall system robustness.

This article presents various scenarios, and the test architecture to robustly detect scan coverage – including potential race conditions – on asynchronous paths.

The salient features of this architecture are:
 • Targets coverage on internally generated set and reset logic
 • Avoids glitches due to reconvergence on scan-enable and async-SE signals
 • Reuses scan-in pin during capture to delay the async-SE trigger

Coverage loss with test-mode gating
A design can have reset logic generated from combinational decoding of other sequential cells, in addition to a top-level reset control. During scan-mode, if this logic gets random scan-data, the sink flop can get reset thus corrupting the scan shift data. To avoid this situation, the combinational logic is gated-off with a static signal (testmode/scanmode) to feed a constant data during shift as well as capture.

However, using a static signal blocks the observe cone of the combinational logic, leading to coverage loss, as seen in figure 1.

To recover this loss of coverage, we typically bypass the internal reset with external pin-reset. The bypassing signal is toggled in one of the scan-modes to allow functional path to propagate to scan-flops as shown in figure 2.

Coverage recovery with scan-enable logic

The coverage loss on functional reset can be recovered, if the gating logic is enabled only during shift. During capture, the functional values take control of the flop-reset pin.

The scan-enable signal (denoting the shift or capture phase) is gated with a static Test Data Register (TDR) bit, so that this functionality is enabled only in a specific ATPG mode (when reset coverage is targeted). The TDR bits needs to be kept out of scan with clock/reset gated, so that the bit retains its value during entire scan operation.

The waveforms in figure 4 shows a window after the clock pulses and before asserting SE, where all glitches in the combinations logic has settled before the logic is made transparent for flop reset pin.

Glitches due to reconvergence on scan-enable cone