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FPGA-killer sol'n combines ARM processor, DSPs, accelerators

Posted: 23 Apr 2015     Print Version  Bookmark and Share

Keywords:Texas Instruments  ARM  processor  DSP  FPGA 

Texas Instruments (TI) has unleashed a multi-processor solution that brings new meaning to downsizing, targeting massive avionic, military, test and measurement and medical instruments, from backpack radars to portable magnetic resonance instruments (MRIs). According to TI, the Keystone-II (66AK2L06) solution allows devices using it to be 66 per cent smaller, use 60 per cent less power, cost 50 per cent less and are three times faster to market than using an FPGA solution.

"Our newest Keystone II SoC has two ARM Cortex A15 MPCore processors, four 1.2GHz C66x DSPs and four programmable accelerators," said Robert Ferguson, communications processors business development manager at TI.

Keystone-II (66AK2L06) solution

TI's FPGA-killer is an SoC with two ARM cores, four DSPs and four programmable hardware accelerators all connected by TeraNet on-chip and by four lanes of 7.8Gb JESD204B interfaces off-chip. (Source: TI)

That spells significant system-level savings for high-speed data acquisition when paired with 4-lanes of JEDEC-compatible input/output (I/O) running at 7.3Gb/s per lane (JESD204B).

The four on-chip accelerators are connected to the other six cores, and each other, with TI's on-chip TeraNet. The four accelerators include a programmable digital-radio front-end (DFE), two programmable Fast Fourier Transform coprocessors (FFTCs), a programmable security accelerator for high-speed encryption/decryption and a packet accelerator for network coprocessor (NETCP) for operations such as header matching and packet modification operations, connected to four gigabit Ethernet (GbE) modules to send and receive packets.

Typical configuration for T&M, avionics and defence apps

Typical configuration for test and measurement, avionics and defence applications (Source: TI)

"The DFE gives us the capability for 48 high-speed digital down converter/up converter channels (DDUC) that also handle digital filtering," noted Ferguson.

TI is also supporting its latest Keystone II offering with its complete suite of software development tools as well as a full reference design, which can be downloaded for customising or purchased on a multi-tier board ready-to-run.

The Keystone-II 66AK2L06 consumes just 12W, a fraction of what an FPGA-based solution consumes, "enabling up to a 50 per cent cost and power reduction compared to FPGAs," said Sameer Wasson, GM of communications processors at TI. "We believe customers will be able to develop their devices three times faster than when using FPGAs, in days rather than weeks."

TI's Keystone-II SoC also is pre-validated for use with TI's family of analogue front ends (AFEs), analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs) including the 12bit, 4GSPS ADC12J4000, the 16bit, 250MSPS ADS42JB69 as well as TI's high-speed DACs, such as the 16bit, 2.5GSPS DAC38J84 as well as TI's clocks, including the LMK04828 clock jitter cleaner. It also can make use of TI's Multicore software development kit (MCSDK) and its RF software development kit (RFSDK).

- R. Colin Johnson
  EE Times

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