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Automating IP handling in a multi-source environment

Posted: 15 Apr 2015     Print Version  Bookmark and Share

Keywords:FPGA  IP cores  Synplify  synthesis tools  RTL 

Once the IP has been imported into the project, it can be optimised within top-level design synthesis in Synplify Premier. This helps to improve overall design timing and area Quality of Results (QoR). The best method to incorporate this IP into your design will involve trading off several factors, including your design performance, power, and area objectives, how the design is to be verified, and how the IP is packaged and formatted. Synplify synthesis tools help designers quickly handle many of the common challenges they face, like how to:

 • Obtain initial timing and area estimates and a modular verification flow.
 • Preserve pre-validated IP while attaining good timing and area that maintains IP boundaries.
 • Gain best timing and area results and optimising RTL and netlist-level IP contents during synthesis.
 • Handle IP that has been packaged to include constraints using special IP constraints and passing important constraints onward to the place-and-route (P&R) tools.
 • Incorporate IP that was delivered to you in encrypted form.
 • Create and package IP for re-use and secure distribution.
The key is to be able to easily import IP content and constraints in a way that delivers both the best timing and area QoR with P&R compatibility downstream and optimum automation. Equally as important is the ability to easily export the IP. In addition, FPGA designers need flexibility while dealing with the complexity of multiple IP sources.

About the author
Joe Mallett is a senior product marketing manager for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation within the semiconductor and EDA industries. Before joining Synopsys, Joe was a senior product marketing manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL Synthesis, IP, and Product/Segment Marketing. He holds a BSEE from Portland State University.

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