Automating IP handling in a multi-source environment

There are many sources of IP cores—third-party, FPGA vendors, and internally developed—and being able to import and synthesise these cores is a key requirement.

Figure 1: FPGA design flows must understand IP in many formats from many sources.

While FPGA vendors are getting good at developing software tools, these vendor tools tie use of IP to an individual technology. Therefore, customers are in need of tools that can not only allow for portability of IP across technologies, but that also properly handle the various forms of IP. For example, FPGA design IP may be delivered in plain text RTL or as a gate-level netlist, and it is commonplace to be presented with encrypted RTL accompanied by a plain text netlist.

The Synplify synthesis tools automate much of the handling of design IP by directly supporting vendor IP catalogs like Altera's Megawizards and Xilinx's IP catalogue. The Altera IP handling within the Synplify FPGA tools can infer Megafunctions and are modelled using the 'clear box' and 'grey box' methodologies.

Figure 2: Example IP flows for FPGA vendor tools.

When designers are using the Vivado IP Catalog, it generates IP in RTL format or as a gate-level netlist, and these files—along with IP constraint files—can be directly added to the top-level Synplify project via the Synplify tools. The system translates Vivado XDC constraints into Synplify FDC constraints format for synthesis use. This eliminates the manual IP import and constraint translation process.

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