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Impact of RTL architecture on power estimation

Posted: 02 Apr 2015     Print Version  Bookmark and Share

Keywords:RTL  FIFO  abstraction  Power analysis  memory array 

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of an SoC) must also be designed keeping that goal in mind. This paper demonstrates the advantages of a well defined RTL architecture for power estimation and analysis using a case study of a FIFO design.

Whenever it comes to power estimation and analysis of a design, most of the tools do all sorts of power optimisation. These tools use a variety of methods that are applied at the gate level, such as substituting high Vth cells and inserting clock gates to reduce power. However, these tools alone are not sufficient to meet the low-power requirements of many designs, and a lot still depends on coding architecture.

FIFO
Let's consider a FIFO which can hold 16 data entries, each of 32 bits. Following are the two implementations of such a FIFO design with different levels of abstraction, and the impact on power analysis.

FIFO design with lower abstraction level
Figure 1 shows a coding architecture for FIFO design with lower level of abstraction. In this case, the logic for checking read/write pointers (Logic 1) and the logic for read/write of memory array (Logic 2) are treated separately and row read/write enables are being used as the control signals for Logic 2.

Figure 1: FIFO design with lower level of abstraction.

Snippet of RTL, for such a design shown in figure 1 is given in figure 2 (Logic1) and figure 3 (Logic2).

Figure 2: RTL Snippet for Logic 1.

Figure 3: RTL Snippet for Logic 2.

FIFO design with higher abstraction level
Figure 4 shows a coding architecture for FIFO design with higher level of abstraction. In this case, the logic for checking read/write pointers and the logic for read/write of memory array are combined in a single RTL block.

Figure 4: FIFO design with higher level of abstraction.

Snippet of RTL, for such a design shown in figure 4 is given in figure 5.

Figure 5: RTL snippet for FIFO write logic.

Though the above two designs are exactly the same in terms of functionality, they have different power numbers when analysed.

The RTL which has been written with lower level of abstraction consumes much more dynamic power. Power analysis results for both the designs are given below in the table.

Table: Power Analysis (*evaluated using Calypto).

Conclusion
Based on the above analysis and description, it is clear that RTL coding architecture has a direct impact on power analysis/consumption, so a proper level of abstraction needs to be defined before coding the RTL in order to achieve low power goals at the SoC level.

Reference
[1] Minimising Power Consumption in RTL Designs Using Sequential Clock Gating and Low-Power Synthesis by Calypto Design Systems Inc.

About the authors
Rohit Goyal , Ashish Banga and Rahul Agrawal contributed this article.





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