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Static verification transforms SoC design at RTL

Posted: 19 Mar 2015     Print Version  Bookmark and Share

Keywords:digital verification  SoCs  deep semantic analysis  DSA  EDA tool 

Despite the fact that linting verification tools have been in use for more than 20 years, new data models are needed to deliver giga-scale capacity and performance for current SoCs. The combination of new levels of performance and DSA lets designers get answers in minutes, and helps resolve chip-scale issues quickly that otherwise would have been missed or would have taken days to resolve. For example, undesired combinational loops often arise when an IP block is integrated into the SoC. Without advanced linting tools, such problems would go undetected and ultimately manifest as failures in deployed products.

Preventing SoC re-spins no longer requires the fastest simulator, assertion verifier or static timer tool; or even an all-in-one tool that does a little bit of a lot of things. What SoC design houses need instead to achieve the next breakthrough in verification efficiency for key SoC-verification objectives—such as CDC, and X-safety verification—is to adopt the mindset of deploying the best-in-class solutions with leading-edge performance, capacity, workflow and sign-off quality.

One advantage of this new mindset is that companies and their design managers can more easily create a set of verification objectives that are comprehensive and complete to meet sign-off requirements at the RT level. Once these objectives are defined, the decision makers can use these sign-off criteria to allocate the right mix of resources between the RTL design team and the system-level verification team, both of which are highly focused on top-level functionality and performance.

Without the move from a tools-driven mindset to a verification-objective-driven mindset, the SoC design process will break down. Static methods now shine as objectives have become clearly defined and failure modes deeply understood. A new age of SoC design is beginning with the advent of best-in-class solutions in CDC and early RTL verification. We expect to see newer objectives to be adopted as teams "shift left" to tackle challenges earlier in the design flow.

About the author
Dr. Pranav Ashar is chief technology officer at Real Intent, which makes EDA software design tools to accelerate Early Functional Verification and Advanced Sign-off of digital designs. He has more than two decades of EDA expertise to Real Intent and previously was department head at NEC Labs in Princeton, NJ where he developed a number of EDA technologies that have influenced the industry.


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