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Static verification transforms SoC design at RTL

Posted: 19 Mar 2015     Print Version  Bookmark and Share

Keywords:digital verification  SoCs  deep semantic analysis  DSA  EDA tool 

We are at the dawn of a new age of digital verification for SoCs. A fundamental change is underway. We are moving away from a tool and technology approach—"I have a hammer, where are some nails?"—and toward a verification-objective mindset for design sign-off, such as "Does my design achieve reset in two cycles?"

Objective-driven verification at the RT level now is being accomplished using static-verification technologies. Static verification comprises deep semantic analysis (DSA) and formal methods. DSA is about understanding the purpose and intent of logic, flip-flops, state machines, etc. in a design, in the context of the verification objective being addressed. When this understanding is at the core of an EDA tool set, a major part of the sign-off process happens before the use or need of formal analysis.

The right mix of these two components—DSA and formal methods—significantly reduces the need for dynamic analysis (simulation). Although dynamic analysis continues to have a role, increasingly it is viewed as a backstop and not the main focus of the verification flow. Any simulation must be absolutely necessary and be tied to a companion static analysis step.

In addition, DSA and formal analysis work synergetically to complete sign-off. DSA generates checks that are precisely scoped and well-structured, enhancing formal analysis performance. Likewise, formal analysis helps validate or falsify hypotheses made during DSA. This combination is proving its value for multiple SoC verification objectives.

X-propagation verification is a prime example. RTL simulation is X-optimistic and can hide bugs or cause RTL and gate-level simulation results to differ. It's important for design teams to understand which constructs in their designs are X-sensitive, and how these can be affected by upstream X-sources. Designers also need to ensure that their designs come out of power-up in a known state, in a given number of clock cycles. Also, powered-down blocks must not cause incorrect behavior in the active blocks. The only way to sign-off on X-verification objectives in a reasonable amount of time is by using static analysis based on combining DSA with the proper application of formal methods.

Verifying clock-domain crossings is another example showcasing the value of DSA and formal analysis for SoCs. Although basic failure modes are simple to describe, identifying these failures in real-life RTL so that all potential failures are reported in acceptable run time—without drowning the engineer in noise—is a formidable challenge. This is an area where DSA shines. Real Intent's Meridian CDC tool, for example, performs full-chip comprehensive CDC analysis in a hierarchical and distributed workflow without resorting to abstractions. For full-chip SOC integration, IP block connectivity must be retained intelligently to make sure "sneak paths" that come into play only at the SoC level can be identified. To enable DSA, data models have been developed to represent even giga-scale designs with all the necessary details for comprehensive verification.

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