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Boost mobile device reliability with ECC

Posted: 10 Mar 2015     Print Version  Bookmark and Share

Keywords:memory throughput  battery life  JEDEC  LPDDR4  DRAM 

Because the refresh rates are set very conservatively, a DRAM with ECC implemented can be refreshed at a rate approximately one quarter of what is set forth in the specification. This saves significant power, especially at elevated temperatures. In addition, it could mitigate the performance impact described above, although this would entail changes to the current JEDEC specification (table 2)

For automotive or other applications that require operating temperatures above 105°C, a DRAM with ECC may be the only practical choice. An LPDDR4 device with ECC can operate in the 115°C–125°C range with the same refresh performance as a non-ECC device does in the 95–105°C range.

Table 2: Proposed changes to the current JEDEC specification.

Why ECC now?
With the added reliability and lower standby power enabled by ECC, it's reasonable to ask why ECC hasn't been introduced to mobile memory technology sooner. Attempts have been made, but they fell short because of the need to support masked write operations.

In brief, write masking allows the memory controller to alter only part of a memory burst, commonly referred to as a prefetch. Without ECC this doesn't pose a problem; the un-masked data bits are written, and the masked bits are not. With ECC, however, writing part of the code word is not an option because the parity bits need to be modified to be accurate for the entire code word. Data masking is required with 8bit granularity. This does not make for an efficient ECC code word size since a Hamming code to correct 8 bits requires 4 parity bits—or a 50% array size overhead. Clearly another method needed to be developed.

To address this issue, the LPDDR4 specification introduces a MASKED WRITE command. This allows the DRAM to perform an internal read-modify-write. In this case the memory contents are read, only the un-masked data is changed, the parity bits re-computed, and the result is written back to the memory array. The result is that only 8 parity bits are required for a data block of 128 bits, providing a cost-effective implementation that optimises die size and power efficiency.

The trade-off is that the MASKED WRITE command requires additional cycles to perform the read/modify/write operation internally. Applications that do not use masked writes are not affected by this delay yet still receive the full benefit of 128-8 ECC efficiency.

For applications that do use masked writes, the timing delay can often be hidden through parallelism. Specifically, the masked write delay only impacts throughput when the application attempts to make back-to-back masked writes to the same memory bank (figure 3). When masked writes are made singly or to different banks (i.e., bank interleaving), the delay has no impact on throughput.

Figure 3: Timing between masked writes to the same bank (top) and to interleaved banks (bottom).

To provide the most bits for the cost and footprint, it is necessary to drive memory to smaller process technology nodes that can provide higher-density die. Memory manufacturers need to address the many issues that arise from shrinking die using more advanced process nodes. By integrating ECC technology into LPDDR4, memory manufacturers can address scaling and reliability issues in a manner that is transparent to both OEMs and users.

ECC increases reliability by providing the next level of redundancy needed in high-density memories. By improving bit cell reliability through ECC, memory manufacturers are able to move LPDDR4 to more advanced process nodes sooner. This increases density and yields, making LPDDR4 memory more cost-effective. Higher reliability further reduces costs by eliminating single-bit errors and lowering product fallout rates. Given the memory requirements, size constraints, and power limitations of next-generation mobile devices, LPDDR4 with ECC provides an optimal solution that increases memory density and bandwidth while maintaining power neutrality and reliability.

About the author
Dean Gans is a Mobile Systems Architect at Micron. He joined Micron in 1989 as an SRAM product engineer, and his career has spanned SRAM design, CMOS imager product engineering, Verilog test development, enterprise SSD product engineering, and DRAM design. Dean earned a bachelor's degree in electrical engineering from Washington State University, Richland, Washington. Dean is a senior member of the IEEE and a member of Tau Beta Pi. He holds 38 U.S. patents.

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