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Boost mobile device reliability with ECC

Posted: 10 Mar 2015     Print Version  Bookmark and Share

Keywords:memory throughput  battery life  JEDEC  LPDDR4  DRAM 

Whenever data is written to memory, the associated parity bits are updated as well. When the data is read, the DRAM verifies the integrity of the entire 136bit (128 data + 8 parity) code word. If a single bit is detected, such as a VRT bit that arises after mounting, ECC will automatically correct the error. Given that the odds of two single-bit errors occurring in the same code word are extremely remote, ECC technology provides an effective way to eliminate random single-bit errors.

Because ECC is a passive technology, errors are detected and corrected automatically. There is no intervention required by developers. The correction is also completely transparent to the rest of the system.

Another benefit of adding ECC to LPDDR4 is that it can result in a lower total cost of ownership in terms of power, performance, and cost. For example, adding ECC to LPDDR4 causes a modest increase in active power, on the order of 5–7%. This increase arises from the additional memory bits and logic circuitry that is required to store and process the ECC parity bits. At the same time, ECC can result in a substantial decrease in standby and refresh power.

Figure 2: Power comparison of LPDDR4 in low power (top), and medium- to high-power use cases with and without ECC (bottom).

When a device is in sleep mode, DRAM-based memory needs to be regularly refreshed to replace the leakage current from each memory cell. The use of ECC increases reliability, which enables the DRAM to reduce the self refresh rate. For most low-power applications, the added reliability of ECC and its superior standby efficiency outweigh the slightly higher active current (figure 2: Standby vs. Active). The power efficiency of LPDDR4 with ECC also helps OEMs achieve power neutrality in next-generation devices; that is, they can provide greater functionality without needing a larger battery or negatively impacting operating life.

In terms of performance, with ECC there is a small amount of additional read latency, which is accounted for in the specified read latency values. Additional write delay is also needed to allow the DRAM time to calculate the parity bits. This time is reflected in the 18ns tWR specification (compared to 15ns for LPDDR3).

Some in industry have contemplated moving to a tWR specification of 45ns to address scaling issues. The inclusion of ECC could mitigate the necessity for this increase in the LPDDR4 specification. This mitigation of tWR increase can more than make up for the performance lost due to the small amount of additional read latency.

ECC also requires a modest increase in die size to accommodate the parity bits and ECC logic. However, these costs should be easily mitigated by higher reliability for OEMs, as well as higher yields and reduced test costs for DRAM manufacturers.

ECC can also improve LPDDR4 performance at high temperatures. DRAM refresh requirements approximately double for every 10°C increase in temperature, and the standard maximum temperature for DRAM is 85°C. Mobile DRAM is no exception; while operation up to 105°C is generally supported, the refresh is specified at 85°C. For operation at 85–95°C, the refresh rate (tREFI) provided by the memory controller must be doubled, and for operation at 95–105°C, it must be quadrupled. This means an 8Gb LPDDR4 memory operating at 95–105°C will require an all-bank refresh command over 18% of the time—time that cannot be used to perform useful functions—and will consume significant power (table 2). It might be possible to perform per-bank refreshes in the background, but these would need to be almost continuous. Of course these conditions will get worse with future higher-density devices.

Table 1: LPDDR4 and LPDDR3 Performance Comparison.

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