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EE Times-India > EDA/IP

FD-SOI gets approval from Freescale, Cisco, Ciena

Posted: 02 Mar 2015     Print Version  Bookmark and Share

Keywords:FD-SOI  28nm CMOS  FinFET process 

With the current chip, "I'm seeing half to a quarter of the leakage power in 28nm FD-SOI [compared to bulk], and...I can change the voltage a lot," said Wolski, noting the chip's ability to run without a fan in an industrial automation system.

"Power was so low with this device we were able to kill another program and subsume its function into this ASIC—that was powerful from an economic point of view," Wolski added.

Similarly, Ciena, too, is using FD-SOI.

"FD-SOI delivered on power, analogue performance and most importantly cost reduction," said Naim Ben-Hamida, a high-speed analogue design manager at Ciena, describing the company's 100 Gbit/s coherent optical transceiver made in the process.

Transistor performance was up to 30 per cent better on FD-SOI than bulk. The process also used fewer masks, had better yields and the same metal stack as bulk, Ben-Hamida said. "Effectively FD-SOI gives us an extra gate to modulate the performance, controlling pmos and nmos transistors...but the tools are lagging; it seems like the key is EDA tool availability," he said.

The optical transceiver essentially combined functions of previous 32nm and 65nm chips and an FPGA "combined in a chip with a third of the combined power of all three," he added.

Representatives of both Cadence and Synopsys were on hand detailed their support for FD-SOI in tools and intellectual property blocks.

STMicroelectronics hopes to have a 14nm version of the process in production before the end of the year. It is optimised for low die cost, but will not match 16/14nm FinFET processes in density.

It's not clear whether engineers will be able to carve out a value added space for FD-SOI at 12nm or 10nm, although engineers are researching the node, said Giorgio Cesana, an ST marketing director and executive co-director of the SOI Consortium. A 7nm version is unlikely, he added.

The 28nm node appears to be a sweet spot for the process, one STMicroelectronics hopes to attract a wealth of designs aimed at the Internet of Things and other applications. At both the San Francisco event and a similar event in Tokyo earlier this year, ST also pitched FD-SOI for some network infrastructure and automotive applications.

According to ST, specific areas where FD-SOI can improve networking infrastructure chips, for example, include better performance and power efficiency, and ability to adapt power consumption to load. Also, a low soft-error rate enables simpler ternary content-addressable memory (TCAM) design, the company said. TCAM is a specialised type of high-speed memory that searches its entire contents in a single clock cycle.

Traction for the FD-SOI 28nm process is gaining said two industry experts familiar with the technology, asking not to be named. However, FinFET-based nodes will act as a mainstream going forward given their superior performance and the lack of an FD-SOI road map to 7nm or beyond.

- Junko Yoshida
  EE Times

—Additional reporting by Rick Merritt and Richard Quinnell

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