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5G by 2020: Realising rapid 5G system development

Posted: 02 Mar 2015     Print Version  Bookmark and Share

Keywords:5G Radio Access Network 

New architectures including Cloud RAN and Virtual RAN take a more centralized approach for greater CapEx (capital expenditure) and OpEx savings. Centralizing base band processing and backhaul functions to serve many hundreds or thousands of remote radios enables the use of GPU-centric server farms with localized data-centre processing at the edge. This change places significant challenges on the fronthauling aspects of the networks, where the data from many hundreds of radios must be transmitted to data centres over various media (e.g., copper, fibre, over the air). 5G infrastructure will also push in other directions—including core virtualisation components such as Software Defined Networks (SDN) and Network Functions Virtualisation (NFV)—resulting in a more software-centric, server-based architecture that allows use of commodity servers and distributed processing.

Implementing Massive MIMO today
The benefits of Massive MIMO are undisputed, but the cost of implementing Massive MIMO is enormous due to the computational burden involving large matrices and linear algebra for beam-forming calculations for each antenna. As a result, Massive MIMO will hugely increase both connectivity and signal-processing requirements. High-speed connectivity is required between the digital front-end (DFE) processing and the analogue domain—many of the data converters are migrating to JESD204B—and between the base band processing and the radio processing, which require some form of serial transceiver. DSP for DFE and beamforming algorithms demands wide bandwidths and high sample rates, necessitating agile, high-performance signal-processing.

Figure 2: Massive MIMO concept leveraging FPGAs and APSoC.

Today, Massive MIMO antenna algorithms can be realised with current technology, as shown in figure 2, but as Massive MIMO systems scale to larger and larger arrays of antenna elements, greater levels of integration will be required. This will be made possible by future device generations.

FPGAs and SoCs enable massive connectivity and capacity
The capacity and latency goals that 5G demands will have a knock-on effect to the requirements of the infrastructure equipment. 5G systems must support massive connectivity and massive capacity that can only be served through the use of high-throughput communications. including 10Ge, 40Ge, PCIe, and future evolutions of CPRI. Capacity increases will come from new modem architectures, advanced radio technology, and new modulation schemes—all of which require huge increases in signal processing capabilities.

FPGAs have long been used in wireless infrastructure equipment due to their high performance, which permits rapid implementation of complex signal-processing algorithms. For example, the latest Xilinx 20nm UltraScale FPGA devices can support over 8 TMACS and more than 5Tbps of serial transceiver bandwidth. Xilinx All Programmable SoC devices couple high-performance FPGA fabric with a fully-integrated processing sub-system based on dual ARM Cortex A9 MPCore processor's, which can be used to efficiently implement higher layers of the complex 5G protocol stacks.

High-end fronthauling
Fronthauling is an evolving market that is driven heavily by the centralisation of base band processing, which—in turn—drives the need for IQ data fronthauling by wireless, copper, or fibre media. Current connectivity standards exist in the form of CPRI and OBSAI. Figure 3 shows a state-of-the-art CPRI aggregator implemented in an FPGA.

Figure 3: FPGA implementation of CPRI fronthaul aggregator.

5G is likely to have a different implementation for some processing elements. For example, Layer 1 base band processing may move to the radio to reduce overall payload bandwidth, which drives greater integration in the radio domain. Whether Layer 1 is integrated within the radio or not, 5G development will continue to focus on base band processing and the radio and on associated fronthauling technologies.

Advanced physical layer evaluation tool flows
Development of the physical layer for 5G is underway with many candidate technologies. Evaluating the relative merits of new candidate air-interface technologies and their associated Layer 1 processing needs is best done with FPGAs, which enable rapid implementation of required algorithms and interfaces. The inherent re-programmability of FPGAs permits rapid design changes to demonstrate improvements or to add features with very little schedule impact.

High-level synthesis (HLS) tools ease development of advanced 5G algorithms. For example, Xilinx's Vivado HLS enables algorithm developers and system architects to design in C/C++ and then synthesise to RTL as shown in figure 4. Popular third-party tools—including MATLAB and Simulink—can also be used for front-end design.

Figure 4: 5G IP creation using C/C++, RTL, or System Generator for Simulink.

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