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Understanding DFI integration with WIDE-IO

Posted: 24 Feb 2015     Print Version  Bookmark and Share

Keywords:DDR PHY Interface  DFI  PHY  DRAMs  memory 

One can enhance or modify the plan requirements hence coverage also as per the features required in the DUT. After implementing the functional coverage infrastructure, map the plan items to be implemented in coverage infrastructure. The result is a traceable, predictable verification plan environment that can assess and refocus on the verification effort accordingly.

Protocol integrity
It can be measured and controlled by the density of assertions and logging assertion passes as well as failures.

Figure 4: Functional Coverage view of WIDE-IO DRAM in coverage window of simulator.

One can use WIDE-IO VIP which comes with an in-built checker which continuously monitors the bus and fires an assertion or error message whenever any illegal activity takes place on the bus.

To Debug the Assertions in Questa GUI without using waveforms invoke the assertion browser by selecting the assertion browser through the menu: view->coverage->Assertions.

The assertion browser shows a listing of all assertions in the design. When an assertion fails, it is easy to identify by the colour red.

Figure 5: The protocol checks can be viewed in Assertion Tracking Window.

Conclusion
We proposed an architecture where WIDE-IO DRAM can be hooked up with DDR PHY. This paper defines the various DFI signals valid for WIDE-IO DRAM along with the various concepts like Initialization, RESET on-off, Activation, Write, Read etc. This model is helpful in development of verification components such as coverage collector and protocol checker in a DFI with WIDE-IO verification environment and thereby reducing the verification efforts.

References
[1] https://www.ddr-phy.org
[2] Preliminary DFI 4.0 Specification Addendum to DFI 3.1 Document
[3] WIDE I/O SDR JEDEC standard JESD229-2

About the authors
Nikhil Jain is working as Lead Member Technical Staff in Questa Verification IP team at Mentor Graphics India Pvt. Ltd., specializing in the development of DDR2, DDR3, LPDDR2, LPDDR3, WIDE IO and WIDE IO2 verification IP. He received his B.Tech degree in Electronics and Communication from GGSIPU University Delhi in 2007.

Aarti Vijay is working as Senior Member of Technical Staff in Questa Verification IP team in Mentor Graphics Private Limited, Noida. She received B.Tech degree in Electronics Engineering from IIT-BHU, Varanasi in 2011. She has expertise in IP level verification and has worked on DFI, DDR4, DDR3, DDR2, HDMI, USB3.0, USB2.0 and SPI verification IP.


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