Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Memory/Storage

Understanding DFI integration with WIDE-IO

Posted: 24 Feb 2015     Print Version  Bookmark and Share

Keywords:DDR PHY Interface  DFI  PHY  DRAMs  memory 

In this article, we will tackle how we can configure our multiple channel environments that have WIDE-IO and DDR PHY where each independent channel in WIDE-IO communicates with DATA and Control interface of DFI.

The DDR PHY Interface (DFI) is the industry specification that defines an interface protocol between DDR memory controllers and PHYs. It enables the development of systems-on-chip (SoCs) that support the latest DRAM standards. Understanding the DFI from a MC perspective across all frequency-ratio systems can simplify the developments of the verification components for the protocol.

WIDE-IO defines the RAM signalling in terms of channels; a single WIDE-IO device will have four channels. The channels operate independently, with the exception of a shared reset signal. A system can organise the memory channels as four "independent"128bit memory interfaces or "combined" as a single 512bit memory.

Figure 1: Architecture showing WIDE-IO Memory Controller communicating with DDR PHY for all channels.

The DFI specification requires a DFI clock and DFI signals must be driven with referenced to rising edge of the DFI clock. This specification is organised in number of interface groups, each interface group consist of signals and its corresponding parameters.

The various interfaces in DFI and their corresponding signals applicable for WIDE-IO DRAM are shown in table 1.

Table 1: DFI interfaces.

The DFI clock and the DFI PHY clock must be phase-aligned and at a 1:1 or 1:2 or 1:4 frequency ratio relative to one another. Some DFI signals from the MC to the PHY must communicate information about the signal in reference to the DFI PHY clock to maintain the correct timing information. Therefore, the DFI PHY clock is described in terms of phases, where the number of clock phases for a system is the ratio of the DFI PHY clock to the DFI clock.

For Multichannel environment DFI parameter phychannel_en will be modified as given in table 2.

Table 2: Channel parameter.

Wide IO
The purpose of WIDE-IO specification is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device.

1 • 2 • 3 Next Page Last Page

Comment on "Understanding DFI integration with W..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top