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CMOS image sensors exceed Moore's Law

Posted: 13 Feb 2015     Print Version  Bookmark and Share

Keywords:CMOS  smartphones  solid-state sensors  Moore's Law 

Complementary metal oxide semiconductor (CMOS) imaging chips have exceeded processors and memory as the industry's leader in advanced process technology. This is due to the strong demand for CMOS imaging chips in diverse applications such as personal electronics, medical equipment and automobiles. Apparently, now the innovation has surpassed Moore's Law, according to analyst firm Yole Développement.

Imaging was once done by film, but with the advent of solid-state sensors the technology breakthroughs seem to be growing exponentially, doubling with each new innovation, thus surpassing the traditional interpretation of Moore's Law, argues Yole Développement (Lyon, France) in a new paper. Yole calls this effect "More than Moore."

At the pinnacle of this growth is 3D stacking, the allure of which for imaging chips is downsizing the chip while simultaneously packing more pixels per unit size, thus one-upping processors and memory, which are only now perfecting the through-silicon-via (TSV) notably with Micron's Hybrid Memory Cube. CMOS imaging chips, however, are one-step-ahead perfecting copper-to-copper bonding of wafers containing the interconnection metallisation for pixel arrays and the digital processing layers of the imaging chip on separate layers below the top (pixel) level.

"The interconnection between the upper part of the 3D stack and the lower part is currently done using TSVs. Two vias are needed for each connection and act as a bridge between the two layers. The metal connection between the two vias is done at the surface of the chip," Pierre Cambou told EE Times, co-author of "Status of the CMOS Image Sensors Industry" with Jean-Luc Jaffard, both Yole Développement analysts.

The CMOS imaging industry may make the 3D TSV obsolete—before the processor and memory industry has even widely adopted it—by perfecting a wafer bonding technique that allows the connection between layers to be made with copper-to-copper (Cu-to-Cu) interconnects nearly as small as regular vias.

"A new technique is currently under development called hybrid bonding," Cambou told us:

  • It is called hybrid because the bonding of the upper part of the stack and the lower part comprise the interconnections made of metal. The bond is therefore not only a bonding of silicon oxide (SiO2), but also, at a number of connecting points, a bonding of copper (Cu). The key limiting factor right now is the accuracy of the bonding for such technology to penetrate the market. The advantage of the hybrid stack is a process simplification; it also opens the way for in-pixel connection to the lower part. This could improve the performance of the pixel and help go to the next step down in pixel size.

Sony is still leading the CMOS imaging industry, but giants like Samsung are in close pursuit. Also big players like Panasonic are forming joint ventures with the likes of TowerJazz to offer 12in wafer fabrication with state-of-the-art quantum efficiency and dark current performance at 65nm, and additional 45nm digital technology, and added available capacity of approximately 800,000 8in wafers per year in three manufacturing facilities in Japan, according to TowerJazz.

The stakes are huge. The CMOS image sensor market will reach the historic $10 billion milestone in 2015, according to Yole, and with new applications popping up in automotive, medical and surveillance, while smartphones begin adopting high-definition front facing cameras, the industry is likely to hit the $16 billion mark by 2020.

Click on the following pages to see slideshow.

- R. Colin Johnson
  EE Times

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