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VESA reveals latest Embedded DisplayPort standard

Posted: 11 Feb 2015     Print Version  Bookmark and Share

Keywords:VESA  Embedded DisplayPort  GPU  eDP 1.4a 

The Video Electronics Standards Association (VESA) has recently published the latest version of the Embedded DisplayPort (eDP) standard. The eDP 1.4a enables a higher video data transfer rate for increased panel resolution, greater colour depth and higher refresh rates.

The latest standard incorporates the VESA Display Stream Compression (DSC) standard v1.1, and includes a segmented panel architecture that allows higher panel integration. These and other refinements were made to the eDP 1.4a standard to take advantage of higher GPU video performance and newer display technologies, while also enabling reduced system power and form factor.

The eDP v1.4a standard leverages the VESA DisplayPort (DP) standard v1.3, published in September 2014, as a base specification. That standard's higher HBR3 link rate, which operates at 8.1Gb/s per lane, is now also part of eDP v1.4a. With both HBR3 and the DSC v1.1 standard included, the latest eDP standard can support embedded panels with up to 8K resolution. For embedded display applications, DSC is most often used to decrease video interface data rate or wire count, as well as reduce display frame buffer size, thereby reducing system power usage to extend battery life. It also enables reductions in system complexity and form factor.

eDP v1.4a

The eDP v1.4a specification from VESA supports segmented panel display architectures, which are designed to enable thinner, lighter and lower-cost panels that use less power.

The eDP v1.4a also features "Multi-SST Operation" or MSO, which supports a novel type of display architecture that VESA calls "segmented panel display," which is designed to enable thinner, lighter and lower-cost panels that use less power. In operation, MSO allows the four high-speed eDP data lanes within the eDP interface to be divided up between either two or four independent panel segments. For lower resolutions, two lanes can be used to support two panel segments. This panel segmentation enables a higher level of integration on high-resolution displays; each segment can contain a separate timing controller with integrated source drivers.

eDP 1.4a also includes refinements to the partial update capability for panel self-refresh (PSR) that was introduced in eDP 1.4. Partial update enables the system video processor, or GPU, to update only the portion of the display that has changed since the video frame update, further saving system power.

It is anticipated that eDP 1.4a will be used within systems by 2016. The eDP v1.4a standard is available to VESA members.





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