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Advanced fault models in small-scale CMOS tech nodes

Posted: 05 Feb 2015     Print Version  Bookmark and Share

Keywords:CMOS  defects  Single Stuck-at  Transition Fault  ATPG tool 

With small-scale CMOS technology nodes, the probability of physical defects occurring in the device grows. Such defects cannot be detected with the help of conventional Single Stuck-at and Transition Fault models. Due to this barrier, use of advanced fault model for detection of physical defects becomes necessary.

The ATPG tool supports the following advanced fault models which can target various classes of faults within the design. Ideally, this tool can apply various test pattern sets that can cover possible faults within the design. This test strategy can help one to increase the high defect coverage leading to drastic test quality improvement. As given in figure 1, Path delay, Hold Time, Small delay and Iddq are diverse fault models supported by ATPG tools other than conventional Single Stuck-at and Transition fault models.

Figure 1: Path delay, Hold Time, Small delay and Iddq are diverse fault models supported by ATPG tools other than conventional Single Stuck-at and Transition fault models.

Path delay test
The path delay test targets faults in the critical path design. During the Static Timing Analysis, the information regarding critical timing paths can be extracted. This information is applied to the ATPG tool for targeting those critical paths. As per the following diagram, the clock period of the circuit is 7ns. The total propagation delay for path P3 B-e-f-g-Z is 6ns, so the path P3 has a small timing slack to meet the requirement. Such information on Critical Timing paths need to be extracted from design analysis. The paths can be targeted through the ATPG tool to generate patterns. One can get signoff that the IC can withstand on such critical timing paths, after successfully executing the path delay test. We observed in our analysis that 73 dies passed through the conventional transition, but 2 dies failed the path delay test. Path delay tests can detect defects those might escape transition tests with higher test coverage.

Figure 2: Path delay test.

Hold time test
The hold time test targets the shortest paths which have maximum timing slack in the design. The shortest paths may result in hold time violation. The ATPG tool will target those paths to cover possible occurrences of fast-to-rise and fast-to-fall faults in the design. As hold time violation is independent of clock period, it can also be detected with stuck-at test. There is still the possibility that the path having hold time violation can escape with stuck-at patterns as these patterns might not create conditions or transitions that is necessary to detect hold time violations. The adoption of this new fault model enables us to detect all possible hold time violations effectively and also makes diagnosis quickly and easily. Figure 3 is a representation of hold time ATPG pattern.

Figure 3: Representation of hold time ATPG pattern.

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