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Challenges in implementing USB 3.1 link layer

Posted: 03 Feb 2015     Print Version  Bookmark and Share

Keywords:USB-IF  USB 3.1  protocol  link layer  TX module 

In 2013, USB-IF released the USB 3.1 specification, fundamentally altering physical, link and protocol players to support maximum data rates doubled to with a 10 Gbit/second. The increased clock frequency, wider data path and new 128b132b data encoding presents real challenges in implementing the link layer.

In USB 3.1, the link layer is responsible for speed negotiation, establishing the connection, ensuring the successful packet exchange, error detection and recovery, and power management. At the PIPE4 interface between the controller and PHY, the clock frequency increases from 125MHz to 312.5MHz for 32bit data width to support the 10 Gbit/s rate. The frequency is even higher for 16bit and 8bit PHY data widths.

With a USB 3.0 link, designers could manage, especially in FPGA prototypes, to have the entire internal link data path run at 125MHz. With additional rules and a different scrambler for 10Gbit/s speeds, designers can no longer build a link data path running at 312.5MHz at 32bit. The solution is to reduce the clock speed and widen the main link datapath to 64bit or 128bit and create a separate PHY interface unit (PIU) logic that runs at the PHY clock.

This PIU module is designed to transfer data between PHY clock and link clock. It also implements a PIPE4 protocol for all data widths (8-, 16-, and 32bit) with a low number of combinational logic levels. While the link clock is reduced to 156.25MHz for 64bit, it is still higher than the 125MHz clock for previous max 5 Gbit/s rate.

Figure: Inside the USB 3.1 link layer. Source: Synopsys

With a 32bit data path in USB 3.0, the TX module processes 4B every clock cycle. With a 64bit or 128bit data path in USB 3.1, the TX module process 8B and 16B respectively.

To make the link efficient, designers must minimise the number of IDLE symbols, packing every link command, data packet, training set, and SKP order set as close as possible in every clock. The challenge is in taking into account all supported USB packet lengths from 0 to 1,024B.

In addition, the USB 3.1 specification defines different transmission priorities for each type of data that the link has to follow. With all of the decisions to be made in one clock cycle, this complex arbitration logic needs to be carefully designed.

The RX path presents different problems. The wider data path results a higher latency in the parser logic for detecting incoming packets. Some packets require a response within 400 ns, so the total TX path, RX path, PHY, and protocol delay must be less than 400 ns at 5 and 10 Gbit/s rates. The complexity of the datapath increases but the link timing budget remains the same.

In 8b10b encoding, the link can rely on the K-symbols in the data stream to identify the start or end of a packet. K-symbols are special symbols that can't be encoded as part of a data payload.

In addition, a USB packet may start and end at any position within a data block. Consequently, the link must keep track the boundary of a received payload, based on its declared length, so that link parser logic won't mistakenly detect a new link command or header within a data payload.

These and other changes in the link layer present challenges for SoC and IP designers. The promise for those who work through the challenges is a USB 3.1 link that attains 10 Gbit/s maximum data rates, increases interoperability and reduces integration risk in storage, digital office, and mobile applications.

About the author
Tri Nguyen is an R&D engineer at Synopsys, a provider of intellectual property blocks and chip design tools.





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