Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Embedded

Grasping design capacity in hardware emulators

Posted: 16 Jan 2015     Print Version  Bookmark and Share

Keywords:software  simulators  hardware  RTL  ESL 

Unlike software simulators, whose specifications do not mention limits in design capacity, a primary specification of hardware emulators is the maximum size of the designs they can handle. More to the point, different emulators have different limits on design capacity. Why is this?

Let's first address the concept of design capacity in a software simulation environment. There is a good reason why the vendors of simulators—whether logic simulators at the register transfer level (RTL) and electronic system level (ESL), or gate level, or even analogue simulators—don't specify the maximum capacities of their tools.

A simulator is essentially a software algorithm running on a computer. The algorithm processes data representing a design model described in a design language at one of multiple hierarchical levels as illustrated in table 1.

Table 1: Design hierarchical levels and corresponding description languages.

The data representing the design model resides on the hard drive of the computer. When the simulator is invoked, that data is moved into the host computer's memory. If the entire design fits into the physical memory, the user can achieve the maximum speed of execution for that design with the given stimulus and the specific simulator. If the design is too large to fit in the memory, then only portions of the design will be loaded. When the processing of a particular portion is completed, the algorithm swaps out the processed design portion and swaps in the next design portion.

Clearly, the larger the memory, the larger the size of the design portions that can be moved in and out of memory. Two problems that may arise are excessive memory swapping and/or cache misses, both of which can have deleterious effects on the speed of execution.

The bottom line is there is no hard limit to the design size any given software simulator can handle. Rather, when the design size reaches several tens of million gates, the speed of execution may drop to such an extent that it becomes impractical to simulate. Often, designers of high end processors claim simulation performance of less than one cycle-per-second, which is pathetically slow if the user needs to execute many millions of cycles.

Hardware emulators are a completely different matter and—to further complicate the story—not all hardware emulators are created equal. For this analysis, we can divide them into three main classes: processor-based emulators, custom FPGA-based emulators (also called emulators-on-chip), and standard FPGA-based emulators. The first two are based on custom chips; the third is built using arrays of commercial FPGAs.

Regardless of the type, all three emulators have limits in terms of the maximum design sizes they can handle, though there are differences.

1 • 2 Next Page Last Page

Comment on "Grasping design capacity in hardware..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top