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Enhancing test quality in advanced CMOS nodes

Posted: 23 Jan 2015     Print Version  Bookmark and Share

Keywords:CMOS  IC design  Design for Testability  DFT  SoC 

The complexity and functional frequency of the design are growing tremendously now that we are transitioning towards small-scale CMOS technology nodes. With a shrinking channel length of CMOS devices, the probability of physical defects increases. Consequentially, after the 90nm CMOS technology node, it becomes mandatory to insert Design for Testability (DFT) logic in the design.

DFT provides certain techniques to convert the original design to a testable design. With the advancement in the process technology nodes, there are many much improved and efficient DFT technologies which are developed for better tests. The basic goal of the DFT technique is to avoid any possible test escape (false positives) in the design.

The test escape can cause the erroneous parts to be shipped to the customer along with good parts. The faulty parts may return back during system testing, thus leading to wastage of time, money and resources of the Original Equipment Manufacturers (OEMs) and Electronic Manufacturing Services (EMS) companies. Such types of test escapes can prove to be immensely costly and a hassle to OEMs and EMS companies, so proper test strategies need to be developed to avoid test escapes and improve test quality.

Ideally, the best way to achieve high defect coverage is to apply tests other than the conventional stuck-at and transition tests, which cover different classes of faults in the design. Guidelines which can help improve test quality are discussed below.

Guidelines to ensure test quality
Avoid over-testing during vector generation: A high quality test means a test which is accurate and complete enough to detect all faults which can affect the functionality of the SoC. So the prime idea is to avoid any under/over testing of the logic. Under testing can result into test escapes, while over-testing may lead to unnecessary yield loss. During final production of vector generation, the power budget needs to be considered for reducing the switching activities in test mode. Applying tight power budget constraints can reduce the amount of switching in test mode. The test switching can be reduced to even less than functional switching. Over-constraining the switching activities though can pass the reliability test in test mode, but might fail in the functional mode which would result in yield loss. Such types of over-testing scenarios need to be avoided for better test quality.

Consider timing exceptions while generating at-speed test: ÿSometimes when you forget to consider timing exceptions during at-speed vector generation, ATPG tool might create patterns that exercise the multi-cycle paths and false paths. These patterns will fail on silicon as one might not meet the required timing on multi-cycle path in one clock cycle. This would result in failure even if that path does not violate the timing requirements, which can result in yield loss. Always get a list of complete timing exceptions from STA team and consider them while generating at-speed patterns.

Avoid too many masking of scan cells during the pattern generation process: During ATPG DRC checking, some clock rule and nonscan cell-related DRC checks fail. On failure to satisfy DRC checks, the affected scan cells are constrained to observe X by the ATPG tool, which in turn affects the overall test coverage. One should identify and try to resolve these DRCs which can affect the test coverage.

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