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Verification IP speeds up ASIC, FPGA design

Posted: 11 Dec 2014     Print Version  Bookmark and Share

Keywords:Mentor Graphics  ASIC  FPGA  ASIC  FPGA 

Mentor Graphics Corp. has recently rolled out its Mentor EZ-VIP PCI express verification IP. According to the company, the verification IP minimises testbench assembly time for ASIC and FPGA design verification by up to 10-fold

Verification IP is intended to help engineers reduce the time spent building testbenches by providing re-usable building blocks for common protocols and architectures. However, even standard protocols and common architectures can be configured and implemented differently from design to design. As a result, traditional VIP components can take days, or even weeks, to prepare for a simulation or emulation testbench.

"When designing with the ARMv8-A architecture and ARM CoreLink cache coherent interconnects in mobile, networking and server SoCs, our partners have a choice of PCIe root complex solutions," said Jim Wallace, director, systems and software group, ARM. "ARM has used Mentor's PCIe VIP library running on Questa and Veloce to help verify critical interactions between PCIe and ARM AMBA interface domains to enable rapid deployment and accurate protocol checking."

Unlike traditional verification IP, Mentor's PCIe EZ-VIP is "design-aware," eliminating several time-consuming steps in the testbench assembly process. This fast-forwards verification engineers past tedious configuration and implementation set-up tasks, directly to high-value scenario generation, reducing a process that used to take days or weeks to just hours, indicated the company.





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