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Significance of SRAMs in nextgen IoT and wearables

Posted: 17 Dec 2014     Print Version  Bookmark and Share

Keywords:SRAM  processors  DRAMs  Flash 

Microcontrollers long ago introduced the deep-sleep mode of operation. This mode of operation helps in power savings for applications that are in stand-by state most of the time. The controller can run at full speed during normal operation but goes into a low-power mode afterwards, thereby saving power. It is important that a similar operation is available for interfaced SRAMs too. Asynchronous Fast SRAMs with a deep-sleep mode of operation [5] make it an ideal choice for such applications. These SRAM chips have an additional input pin that helps the user toggle between different modes of operation (normal, standby, and deep-sleep). Thus, effective power consumption can be managed without compromising performance.

On chip error correction capabilities
As memory process technology scales for improved performance and power, reduced voltage and shrinking node capacitance makes these devices more susceptible to soft errors. Today, CMOS technology has shrunk to such a size that extraterrestrial radiation as well as chip packaging cause failures at an increasing rate. Traditionally, soft errors have been dealt with through the use of ECC (error correcting code) software or through redundancy (i.e., multiple SRAMs storing the same data), especially in systems where reliability is of paramount importance, such as medical, automotive, and military systems. However, this is expensive and requires extra board space.

Major SRAM manufacturers have started implementing error correction features directly on-chip [6]. To limit the effects of soft errors on modern semiconductor memories at a chip level, two architectural enhancements are used: on-chip ECC and bit interleaving. Through on-chip ECC, the software to implement error detection and correction of single-bit errors is hard-coded into the SRAM. Some manufacturers even offer the option of an extra error pin to indicate the detection and correction of single-bit errors.

Bit interleaving, on the other hand, is used to limit the effect of multi-bit errors (i.e., a single energetic particle flipping multiple bits). Bit interleaving works by arranging adjacent bit lines to different word registers. This converts a multi-bit error into multiple single-bit errors, which can then be corrected by the on-chip ECC.

SRAMs and the future
Exciting times are ahead for SRAM technology. The technological trends and advancements favour a grand comeback for this technology, whose adoption has been declining for years. ECC-enabled chips are already in production. Fast SRAMs with on-chip power management are also available. Serial SRAMs are in production but mostly for very low density applications and so are currently not comparable in speed to parallel counterparts. However, the existing players in the serial market (Microchip and On-semi) happen to be primarily MCU manufacturers. None of the traditional SRAM companies have launched serial SRAMs yet. With more players entering this market, we can expect innovation to happen rapidly.

Traditional marketing wisdom about product life cycles says that maturity is followed by decline and then death of a product. The negative CAGR of SRAMs, along with the fact that most suppliers have quit the business, would have classified this product as "declining". The revival of SRAMs that we are witnessing today and foreseeing for the future perhaps requires a revision of the traditional concept of the product life cycle in general.

1. Wikipedia: Semiconductor Device Fabrication
2. Scaling Effects on Neutron-Induced Soft Error in SRAMs Down to 22nm Process, by Eishi Ibe, Hitoshi Taniguchi, Yasuo Yahagi, Ken-ichi, Shimbo, and Tadanobu Toba
3. Leakage Current: Moore's Law Meets Static Power, IEEE Computer, January, 2009
4. Application Note AN69601: Guidelines for Cypress Wafer Level Chip Scale Packages
5. Application Note AN89371: Power saving with Cypress Asynchronous PowerSnooze SRAM
6. Application Note AN88889: Mitigating single event upsets using Cypress Asynchronous SRAM

About the author
Reuben George works in Product Marketing for the Memory Products Division of Cypress Semiconductor. He holds a BE in Electrical & Electronics Engineering from the Birla Institute of Technology and Science (BITS), Pilani, in Rajasthan, India.

Anirban Sengupta works as a pricing manager at Cypress Semiconductor. He holds a BE in Electrical Engineering from the National Institute of Technology, India, and an MBA in Marketing from Symbiosis Centre for Management and Human Resource Development (SCMHRD), Pune, India.

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