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Significance of SRAMs in nextgen IoT and wearables

Posted: 17 Dec 2014     Print Version  Bookmark and Share

Keywords:SRAM  processors  DRAMs  Flash 

In the following sections, we describe some of the key innovations in the design of SRAMs that are driving embedded developers to consider their use in their embedded wearable, IoT, and other embedded systems applications.

Chip scale packaging
Chip scale packaging (CSP) [4] is a powerful technique to reduce the size of chips. As per specifications (J-STD-012), to qualify as 'chip scale' the overall packaged part must have an area not more than 1.5 times that of the die and a linear dimension not more than 1.2 times that of the die. In contrast, for a standard packaged die, the overall chip area could be as high as ten times that of the die. Thus chip scale packaging can help reduce the size of a chip manifold. A similar size reduction could be achieved by shrinking the process node. However, in the case of SRAMs, migrating to a smaller process node is fraught with risks, as already explained.

This reduction in area is achievable by eliminating the first level packaging – lead frame, die attach, wire bonds, and mould compound. CSP chips are mostly packaged at the wafer level where the packaging material is deposited directly on the wafer. The pinout is similar to BGA (ball grid array packaging) whereby solder bumps on the package act as pins. A similar size reduction could be achieved by shrinking the process node.

A CSP SRAM would definitely be an excellent fit for space-constrained boards in wearable applications. It is much easier to design-in than the next best alternative: buying an SRAM die and packaging it along with the MCU die using sophisticated MCP (multi-chip packaging) techniques. Currently, CSP SRAMs are not in mass production (some suppliers offer it as a made-to-order option), possibly because the target market (wearables) has yet to move beyond the embedded niche. However, most of the key players in the SRAM market offer a CSP option for many of their other products. Cypress Semiconductor, for example, has CSP versions already available for its product families such as PSoC. Thus, it should not be difficult for manufacturers to extend the same capability to SRAMs.

Lower pin count
While SRAMs consume less power than Flash and DRAM, a key problem of using SRAMs for memory expansion is its parallel interface. While a parallel interface allows faster read-write times, too many IOs are required for interfacing. For example, consider interfacing a 1Mb SRAM (64Kb x16) with an MCU. The number of IOs required would be 32 (16 address, 16 data). Multiplexing could bring that down to 24. But with every subsequent increase in density (2M, 4M, 8M etc.), the number of pins increases by 1.

The number of IOs available to interface with SRAMs in a tiny wearable board is limited because small MCUs have low pin count packaging. To connect with these MCUs, SRAMs will have to move beyond the traditional parallel interface. The success of Serial Flash, EEPROM, etc. reinforce the market's need for a serial memory option.ÿSince MCUs having been using embedded cache for years, the need for serial SRAM has not been felt until recent years. Serial SRAMs make interfacing simpler and less pin consuming (two for single SPI, two for dual SPI, and four for quad SPI). In addition, the number of IOs required does not increase with density.

As of today we have serial SRAMs in low density and comparatively lower access speed (up to 25ns access time and 1M density). In the near future, we can expect improvements in both these parameters. As the wearable products enter subsequent generations, we can expect that MCUs will be required to perform more complex operations. In such cases, it would be useful to have a higher density cache/scratchpad memory with higher throughput. Thus the evolution of serial SRAMs towards higher speed and density will be useful for the market. A size reduction using CSP packaging coupled with serial interface will make SRAMs a powerful option for both cache and scratchpad memory in wearables.

High performance with low power
Today there are two distinct families of asynchronous SRAMs: fast SRAMs (with high access speed) and low-power SRAMs (low power consumption). From a technological standpoint, this trade-off is justifiable. In low-power SRAMs, special GIDL (gate-induced drain leakage) control techniques are employed to control standby current and thus standby power consumption. These techniques involve adding extra transistors in the pull-up or pull-down path as a result of access delay increases, and in the process, increases access time. In fast SRAMs where access time is the priority, such techniques cannot be used. Moreover, to reduce propagation delay, die size is increased. This increase in die size increases leakage and, in the process, the overall standby power consumption.

So far this trade-off was acceptable by typical SRAM applications: Battery-backed applications used Low-power SRAMs (compromising performance) while wired industrial high-performance applications used fast SRAMs. However, for IoT applications and many other advanced applications such a trade-off will not serve well. The main reason is that for most of these applications, high performance is important while standby power consumption has to be limited as well, since most of these applications will be operating on battery power. Fortunately, SRAMs are evolving to bridge the performance gap between these two families towards a single chip with the benefits of both.

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