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Controller IP core supports HMC 2.0, 1.0 data rates

Posted: 24 Nov 2014     Print Version  Bookmark and Share

Keywords:hybrid memory cube  IP core  SerDes 

Open-Silicon released a comprehensive hybrid memory cube (HMC) 2.0 controller solution as licensable IP that will enable SoC designers to take immediate advantage of the performance gains afforded by the emerging memory standard.

The HMC 2.0 memory controller IP is soft macro implementation designed to be compliant with both HMC v1.0 and the upcoming HMC v2.0, supporting all of the defined data rates of both standards. The device seamlessly interfaces to leading third-party SerDes IP without the need for an additional PCS layer.

Supporting data rates of up to 480GB/s, the IP offers a low latency and a flexible user interface. The IP is delivered with a comprehensive set of deliverables including a test bench with a generic HMC model. Moreover, Open-Silicon's recently announced SerDes Technology Centre of Excellence (TCoE) will provide ASIC engineers a way to verify and test the integration of the HMC 2.0 memory controller IP with SerDes.

HMC is a revolutionary innovation in DRAM memory architecture that sets a new standard for memory performance, power, reliability, and cost. Governed by the Hybrid Memory Cube Consortium (HMCC), the specification fundamentally changes the way memory is built into a system by leveraging 3D packaging to connect multiple DRAM arrays to logic using through silicon vias. The HMC 2.0 standard, recently ratified by the HMCC, specifies data rates up to 30Gb/s.

"Our extensive background with both the integration of HMC IP and advanced design techniques is enabling a new generation of ASICs designed to address the growing bandwidth requirements of 100G and 400G networks, as well as high-performance computing," said Hans Bouwmeester, VP of IP and Engineering Operations at Open-Silicon. "As a developer member of the HMCC, we are actively involved in defining the specification, and can deliver standards-compliant IP as soon as the standard is ratified."

HMC controller IP core

The IP is highly configurable with support for a number of different internal and user interface data path widths, allowing designers to tailor the controller to match their performance, area, or power requirements. (Source: Open-Silicon)

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