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Frequency-flexible clock generators for data centres

Posted: 24 Nov 2014     Print Version  Bookmark and Share

Keywords:data centre  LAN  OTN  Cloud  frequency-flexible clock generator 

Therefore, to meet increasing demands for higher network port density and bandwidth in data centre switch blades, clock tree designers need clock generators that offer:
 • Multiple, low-phase jitter SerDes and PHY reference clocks that are fully compliant with the stringent jitter performance specifications required by the dominant networking (1/10/100G Ethernet), storage (Fibre Channel, PCIe) and computing (PCIe, Infiniband) standards. Generally, the jitter specifications range from about 1 ps RMS to less than 300 fs RMS (12 k to 20MHz).
 • Frequency flexibility to enable simultaneous generation of a wide range of integer and fractionally-related clock frequencies while adhering to the stringent network, compute and storage, and clock jitter specifications. The ability to change frequencies on the fly, without affecting other outputs, is also highly desirable. For example, this enables speed-grading CPUs to meet different product cost and market needs.
 • Highest level of integration to provide significant reductions in PCB area, cost and component count and maximise system port densities and cost per bit.

New approach to clock tree design for converged data centers
In contrast to traditional clock generators, next-generation clocking solutions, such as Silicon Labs' Si5341/40 clock family, leverage fractional- and integer-frequency-synthesis flexibility and higher levels of integration. This architectural approach delivers a single-chip solution that integrates all discrete timing functions into a single IC. Silicon Labs' proprietary MultiSynth fractional divider technology is touted as key to enabling the Si5341 clock to simultaneously generate any integer or fractional frequency up to 800MHz on any output, with typical jitter < 150 fs.

As shown in figure 4, the Si5341 clock uses a single, low-power VCO to drive five independent MultiSynth fractional dividers, which are connected via a non-blocking cross point switch to an array of 10 clock outputs. In the first stage of this architecture, the MultiSynth high-speed fractional-N divider switches between the two closest integer divider values to produce an exact output clock frequency with 0 ppm frequency synthesis error. To eliminate phase errors generated by this process, MultiSynth calculates the relative phase difference between the clock produced by the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform.


Figure 4: Si5341 functional diagram.

This approach makes it possible to generate any-output clock frequencies from 1kHz to 800MHz with 0 ppm error. The result is better than 100 fs RMS phase jitter performance (12kHz to 20MHz) in integer mode and less than 150 fs in its synthesis mode, which simultaneously generates both fractional and integer-related clocks.

Frequency flexibility transforms clock tree designs
By using the frequency-flexible, ultra-low jitter, 10-output Si5341 clock generator, developers can reduce the clock tree for a data centre switch blade from eight discrete components to just one clock (figure 5).

 Traditional vs. Si5341-based clock tree

Figure 5: Traditional vs. Si5341-based clock tree.

Cloud-based streaming services are driving growing demands for higher data rates. To meet these demands, high-speed networking and data centre equipment requires frequency-flexible clock generator IC solutions to support faster data rates.

About the author
Phillip Callahan is a senior marketing manager.

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