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Xilinx rolls IDE for OpenCL, C and C++, targets data centres

Posted: 19 Nov 2014     Print Version  Bookmark and Share

Keywords:Xilinx  data centre  FPGA  IDE  CPU 

Xilinx Inc. has recently unleashed the SDAccel integrated development environment (IDE) for OpenCL, C and C++. As the latest member of the SDx family, SDAccel combines the industry's first architecturally optimising compiler supporting any combination of OpenCL, C and C++ kernels, together with libraries, development boards and the first complete CPU/GPU-like development and run-time experience for FPGAs, stated the company.

SDAccel's architecturally optimising compiler claims to deliver up to 25 times better performance/watt compared to CPUs or GPUs and three times the performance and resource efficiency of other FPGA solutions, flaunted Xilinx. SDAccel leverages foundational compiler technology that is used by more than 1,000 programmers. It harnesses the power of this complier and enables software developers to leverage new or existing OpenCL, C and C++ code for creating high performance accelerators, optimised for memory, dataflow and loop pipelining in a range of data centre applications such as compute search, image recognition, machine learning, transcoding, storage compression and encryption.

With SDAccel, developers can use a familiar workflow to optimise their applications and take advantage of FPGA platforms with no prior FPGA experience. The IDE provides coding templates and software libraries, and enables compiling, debugging and profiling against the full range of development targets including emulation on x86, performance validation using fast simulation, and native execution on FPGA processors. The IDE executes the application on data centre-ready FPGA platforms complete with automatic instrumentation insertion for all supported development targets. SDAccel has also been architected to enable CPU/GPU developers to easily migrate their applications to FPGAs while maintaining and reusing their OpenCL, C and C++ code in a familiar workflow, Xilinx indicated.

The comprehensive SDAccel environment includes the programmer-ready IDE, C-based FPGA optimised libraries, as well as commercial off-the-shelf (COTS) platforms.

SDAccel development environment

SDAccel combines an architecturally optimising compiler supporting any combination of OpenCL, C and C++ kernels, together with libraries, development boards and the first complete CPU/GPU-like development and run-time experience for FPGAs.

SDAccel libraries include OpenCL built-ins, DSP, video and linear algebra libraries for high performance, low power implementations. For domain specific acceleration, optimised OpenCV and BLAS OpenCL compatible libraries are available from Xilinx Alliance member Auviz Systems, Initial COTS members include Alpha Data, Convey, Pico Computing with more being added in early 2015.

Only SDAccel supports large applications with multiple programs and CPU/GPU-like on-demand loadable compute units, the company stated. Unique to FPGA solutions, and like CPU/GPUs, SDAccel keeps the system functional during program transitions. SDAccel claims to be the only environment that creates FPGA-based compute units that can load new accelerator kernels while an application is running. Throughout application execution, critical system interfaces and functions such as memory, Ethernet, PCIe and performance monitors are kept live. On-the-fly reconfigurable compute units allow FPGA accelerators to be shared across multiple applications. For example, operational systems can be programmed to switch between image search, video transcoding and image processing.





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