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Instructions for programming LP8501

Posted: 19 Nov 2014     Print Version  Bookmark and Share

Keywords:LP8501  programming  SRAM  memory  code 

This application note describes LP8501 programming instructions with examples. Most of the programs are presented with command compiler syntax. Command compiler is described in more detail in Using the LP8501 Evaluation Kit (SNVU451). Compiler software is available with the evaluation kit.

Programs here consist of directives, labels, instructions and comments. The machine code, which is loaded into LP8501 SRAM memory, consists of 16–bit instructions. These instructions are written into registers from 50h to 6Fh. In register 4Fh is a page selector with 6 possible pages to choose from (bits '0' to '101' [0:2]). Instructions must be written to two consecutive addresses, like for example 50h and 51h in page 0. These addresses correspond to SRAM address 00h. The paging of SRAM memory is only for I2C communication. When developing the code one can treat the whole memory as a whole. This means that the program code can continue to different SRAM pages. The paging needs to be taken into consideration only when the program code is uploaded via I2C. The paging does not affect program code execution.

View the PDF document for more information.

Originally published by Texas Instruments Inc. at www.ti.com as "LP8501 Programming Considerations".





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