Xilinx's 20nm FPGA offers highest DSP

Augmenting its 20nm portfolio, Xilinx Inc. has introduced the Kintex UltraScale KU115 FPGA. Touted as the flagship of the Kintex UltraScale family, the KU115 provides the highest DSP count available in a single programmable device. This product aims at data centre compute acceleration and signal processing applications including video and medical imaging, broadcast systems and radar.

The KU115 FPGA is optimised for a full range of DSP-intensive operations ranging from floating point to fixed point. Delivering up to 8,181 GMACs for symmetric filtering applications, the embedded DSP block includes enhancements for high definition video encoding, FEC (forward error correction) and CRC (cyclical redundancy check) for wired communications systems and for complex filtering and arithmetic commonly used in wireless communications and aerospace.

With more efficient resource utilisation per operation, the KU115's optimal performance-per-watt meets the needs of processing-intensive systems with stringent power and thermal requirements. Combined with high-level abstraction tools including Vivado High Level Synthesis and Xilinx's software-defined development environment for OpenCL, the family provides a complete solution to minimise compute bottlenecks when designing and implementing DSP-intensive algorithms.

The Kintex UltraScale FPGAs claim to deliver up to 1.16M logic cells, 5,520 optimised DSP slices, 76Mbit/s of block RAM, 16.3Gbit/s backplane-capable transceivers, PCIe Gen3 hard blocks, integrated 100Gbit/s Ethernet MAC and 150Gbit/s Interlaken IP Cores, and DDR4 memory interfaces operating at 2,400Mbit/s.

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Related Terms

What is FEC?
In telecommunication and information theory, forward error correction (FEC) is a system of error control for data transmission, whereby the sender adds redundant data, known as an error-correction code (ECC), to its messages. This allows the receiver to detect and correct errors (with some limitations) without asking the sender for additional data. The advantages of FEC are that a back-channel is not required and retransmission of data can often be avoided though this is achieved at the cost of higher bandwidth requirements. FEC is therefore applied where retransmissions are relatively costly or impossible. In particular, FEC information is usually added to most mass storage devices to protect against damage to the stored data.
For instance, electrical or magnetic interference inside a computer system can cause a single bit of DRAM to flip to the opposite state. This problem can be mitigated by using DRAM modules that include extra (redundant) memory bits and memory controllers that exploit these bits. These extra bits are used to record parity or to use an ECC. Parity allows the detection of an odd number of wrong bits. The ECC may allow a single-bit error to be corrected and double-bit errors to be detected.
Error detection and correction in computer systems keeps going in and out of vogue. Seymour Cray famously said "parity is for farmers" to explain why he left it out of the CDC 6600. He included parity in the CDC 7600, and reputedly said "I learned that a lot of farmers buy computers."

What is FPGA?
Short for Field-Programmable Gate Array, a type of logic chip that can be programmed. An FPGA is similar to a PLD, but whereas PLDs are generally limited to hundreds of gates, FPGAs support thousands of gates. They are especially popular for prototyping integrated circuit designs. Once the design is set, hardwired chips are produced for faster performance.

Xilinx's 20nm FPGA offers highest DSP

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