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Building high-reliability FPGA designs

Posted: 31 Oct 2014     Print Version  Bookmark and Share

Keywords:FPGA  single event upset  SEU  triple modular redundancy  finite state machines 

Over the recent years, the need for high-reliability and high-availability systems has expanded past military and aerospace into the data center, onto the industrial floor, and into medical devices. This challenges FPGA developers to build highly reliable systems to address the growing market needs. There are several special design techniques that can be used to detect in-system errors and recover to correct operation.

Soft errors
With increasing integration of electronics for things like engine control, braking systems, and collision avoidance in automobiles, there is little-to-no margin for soft errors that could result in harm to humans. There are other applications that may not endanger lives, but still require safe operation, like medical equipment, industrial control, and high-availability communications equipment that could be very costly when a system fails. The challenge is that all electronic equipment can be affected by radiation-induced "glitches," advanced process technologies, and complex system implementation.

Today, many FPGAs are used to implement critical functions in electronic systems, and, as a result, it is critical to make sure they operate correctly and reliably. Radiation in the atmosphere can cause unstable conditions that result in an unwanted transient signal in the combinatorial logic of an FPGA. If this transient—known as a single event upset (SEU)—is propagated throughout the system, it could potentially cause a failure.

Figure 1: Example SEU in memory storage.

A propagated error can cause an error unless there is a built-in mechanism for error detection and correction. Synplify Premier software has built-in safety features to help mitigate SEUs and achieve greater design reliability by automatically replicating parts of the circuit to create triple modular redundancy (TMR). The tools insert redundancy automatically into the design by tripling all, or part, of the logic in a circuit, and then adding in "majority voting" logic to determine the best two out of three results.

Figure 2: Inserted redundancy with tripled circuitry and voting logic.

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