DDR memory test: Achieve accurate, repeatable results

Since it was introduced as a standard in the mid-1990s, dual data-rate (DDR) SDRAM memory has been employed in almost all computing applications. Compared to single data-rate SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals.

Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a SDR SDRAM running at the same clock frequency, due to this double pumping.

The strict control of clock and data timing leaves relatively little margin for error in a DDR SDRAM interface. Testing of these interfaces demands adherence to some important best practices to ensure accurate and repeatable results. Let's look at a few of these best-practices, beginning with some recommended mechanical probing techniques.

First, what does a typical DDR test configuration look like? Figure 1 shows an example of a test configuration for a desktop computer platform, while figure 2 shows the setup for a netbook computer. Refer to the images for some notes on the setups.

The first recommended technique makes use of a hands-free probe holder mounted in reverse position (figure 3). This configuration provides much-needed strain relief for the probe connections. The probe holder acts as a counterweight, removing force from the probe tip. Another recommended technique for strain relief is to employ a gooseneck device to support the probe tips. This is achieved by mounting an adhesive base on a chip in close proximity to the DUT. A third technique is to use a chip clip to secure a probe to a board or chassis. The clip prevents movement of the probe platform's cable assembly.