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Solution eases verification closure for complex SoCs

Posted: 16 Oct 2014     Print Version  Bookmark and Share

Keywords:Synopsys  SoC  verification closure  FPGA  prototyping 

Synopsys Inc. released the Verdi Coverage advanced planning and coverage technology to improve verification closure for complex SoCs. According to the company, the advanced solution allows users to quickly create efficient verification plans, assimilate third-party and user-defined metrics, link plans to requirement documents, and intuitively track project and test-level metrics across simulation, static checking, formal verification, VIP and FPGA-based prototyping.

Verdi Coverage enables users to understand project progress, manage regression data, launch verification jobs, track project trends, generate reports and ultimately optimise resource allocation.

Synopsys' innovative planning and coverage analysis technology is built on top of the Verdi environment recognised for being optimised, extensible and easy to use. Fully integrated with all Verdi debug views, it allows users to quickly analyse and cross-probe any holes identified through coverage analysis. It is also interoperable across a range of solutions. This level of integration and interoperability provides a unified view of project status that allows users to focus only on tasks required to improve the predictability of verification closure, according to Synopsys.

Verdi Coverage is available in limited customer availability (LCA). The advanced planning and coverage technology is also included as part of Synopsys' Verification Compiler product, also in LCA. Both products are planned for general availability in December 2014.

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