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Support halves MIPI D-PHY area, power consumption

Posted: 18 Sep 2014     Print Version  Bookmark and Share

Keywords:MIPID-PHY  physical layer  Synopsys 

Synopsys rolled out the DesignWare MIPI D-PHY, which has an area and power consumption that is lower by 50 per cent compared to competitive solutions.

According to the company, the new physical layer design also delivers aggregated data throughput of up to20Gb/s per lane, while also reducing SoC silicon cost and extending battery life for mobile, consumer and automotive applications.

It is the first D-PHY that is compliant to the MIPI Alliance D-PHY v1.2 specification and part of a complete solution with DesignWare MIPI DSI and CSI-2 controllers and verification IP (VIP), reducing integration risk and the effort of connecting to a variety of image sensors and displays.

"The DesignWare MIPI D-PHY offered low power consumption, high performance and configurability options that were critical to the success of our Myriad 2 Vision Processing Unit," said Sean Mitchell, senior vice president and COO at Movidius.

The DesignWare MIPI D-PHY is the physical layer used for MIPI CSI-2 and DSI host and device applications to connect image sensors and displays to SoCs in mobile and embedded applications. For high-resolution output, four lanes of the DesignWare MIPI D-PHY can be aggregated to support 10Gb/s speeds and eight data lanes can be aggregated to achieve 20Gb/s speeds. It's configurability options also enable designers to reduce the number of SoC designs required to target multiple applications, minimising time-to-market.

The new DesignWare MIPI D-PHY is available in 16nm FinFET processes, while 28nm processes are scheduled for next year.

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