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SerDes platform eases ASIC dev't for 100G networks

Posted: 17 Sep 2014     Print Version  Bookmark and Share

Keywords:SerDes  100G  SBMULTC2T28HPM28G 

Open-Silicon unveiled a 28Gbit/s Serialiser/Deserialiser (SerDes) evaluation platform for ASIC development that will enable the rapid deployment of chips and systems for 100G networks.

The platform includes a full board with packaged 28nm test chip, software, and characterisation data. The chip integrates a 28Gbit/s SerDes quad macro, using physical layer (PHY) IP from Semtech, and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR, and CEI-28G-SR specifications.

"Silicon-proven IP, such as the advanced 28Gbit/s SerDes PHY developed by Semtech, is central to our success as a leading ASIC solutions supplier," said Taher Madraswala, president of Open-Silicon. "In selecting IP and IP partners, we take into account not only the overall functionality within the IP and its compatibility with other IP blocks, but also its interoperability within the ASIC tool flow and how reliably it can be manufactured in a high-volume process technology."

The Semtech SBMULTC2T28HPM28G PHY has an analogue front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing. The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis, and pre-emphasis. The PHY can be programmed to support multiple standards each with specific electrical performance characteristics. The area, power, and latency have been optimised for use in SOCs, ASICs, or ASSPs. A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments.

As part of the Open-Silicon SerDes Technology Center of Excellence (TcoE) offering, the 28G SerDes is targeted for ASIC and SoC deployment in high-data-rate, chip-to-chip, and chip-to-module applications. Open-Silicon applies its unique, high-speed serial design expertise to ensure the successful delivery of ASICs and SoCs for next-generation, high-speed systems used in the networking, telecom, computing, and storage markets.

The 28nm test chip has been packaged in a 19mm x 19mm, 324-ball high performance Low Temperature Co-Fired Ceramic (LTCC) Flipchip substrate. This package material was selected for its relatively wider trace characteristics, low loss tangent, and superior uniform via arrangements that minimise reflections in vertical transitions. Open-Silicon optimised the final package design through simulations to meet and exceed the guidance derived from the CEI specifications.

The 28Gbit/s SerDes evaluation platform will be available by the end of Q3.

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