Tabula pushes packet rates at 100Gbit

Programmable logic solutions provider Tabula made the headlines in the past for its innovative 3D Spacetime FPGA architecture, the resulting ABAX² series of general-purpose 3PLDs, and the associated Stylus tool suite.

The use of a 12-level third dimension dramatically shortens interconnects, yielding faster and more efficient place-and-route, simpler timing closure, and higher resource utilisation. As when designing with regular FPGAs, designers capture the design functionality using standard Verilog or VHDL and invoke Tabula's Stylus tool suite to compile and place-and-route the design.

More recently, Tabula has given the impression of keeping a low profile. There is a reason for this. Unlike a lot of companies, it typically doesn't like to announce anything until it's ready to start shipping. This explains why today, at the Intel Developer Forum (IDF), Tabula has reappeared on the scene in a dramatic fashion.

Tabula has just announced the first shipments of 100G development systems based on the industry's first 22nm 3PLD, which have been manufactured for it by Intel. The extreme performance ABAX² devices enable deep packet inspection at line rate and the routing and switching of multiple 100G streams on a single chip.

The first board is a low-latency 12 x 10GE-to-100GE Bridge providing transparent bidirectional bridging between the 10GE ports and the 100GE port. This board—which can be easily modified to support different port counts, port speeds, and interface standards—is shipping to customers.