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PCIe3 cores validated on S2C's ASIC prototyping platforms

Posted: 20 Aug 2014     Print Version  Bookmark and Share

Keywords:Northwest Logic  S2C  ASIC  PCI Express  PCIe IP 

Northwest Logic and S2C Inc. have revealed that Northwest Logic's PCI Express (PCIe) 3.0 solution, including the Expresso 3.0 Core (PCI Express 3.0 Controller Core) and family of DMA Cores, has been validated on S2C's ASIC prototyping platforms.

According to the companies, the cores expand S2C's Prototype Ready IP suite. The validation was done with eight lanes running at 8Gb/s SERDES rates. The joint validation effort ensures user's confidence on integrating the high-speed PCIe IP into their SoC designs, shortening the project cycle.

S2C's FPGA-based solutions enable designers to quickly implement and debug their latest high-performance designs, as well as develop and refine system software. S2C's TAI logic module family provides high-speed GTX ports, on-board DDR3 memory and various interface daughter cards for users to easily verify high-performance interface IP such as PCIe, SATA and USB.

PCI Express 3.0 Core

Northwest Logic claims to provide a complete PCI Express Solution. This solution includes Northwest Logic's high-performance, easy-to-use, silicon-proven Expresso 3.0/2.1/1.1 Cores for PCI Express, DMA back-end core that provides high-performance scatter-gather DMA engines, drivers (Linux & Windows) and application software.





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