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Processing horsepower for data stream convergence

Posted: 21 Jul 2014     Print Version  Bookmark and Share

Keywords:thermal management  power dissipation  ARM  Cortex  R-Car 

Of all the hardware accelerators, the 3D graphics processor is the largest in every respect. These are often larger than many CPU cores nowadays, and run at similar clock speeds. They can easily use 30 per cent or more of the overall power consumption. Each new generation has about four times more 3D performance than the preceding one because of the growing use of high-definition screens. Choosing the right accelerator for the processors performance category makes a significant contribution to reducing power consumption. For the new generation of the R-Car family, Renesas is again using IPs from Imagination Technology. The smallest product in the range, the R-Car E2, provides about the same performance as the R-Car M1 the previous mid-range product while the R-Car H2 delivers 8 times more performance, which is four times more than the previous generation while maintaining full software compatibility. A key benefit here is that this increase in power does not come at the cost of power consumption, which has hardly increased at all.

Figure 3: R-Car H2 hardware accelerators.

All these hardware accelerators share their memory with the processors. That enables powerful data transmission between the various components while remaining cost-effective. This is known as Unified Memory Architecture (UMA), but its disadvantage is that the available memory bandwidth can turn into a bottleneck. An increase in the performance of the application processors goes hand in hand with an increase in memory bandwidth, which has to work within tight constraints. Although other applications could get round this issue by simply using wider memory buses, that solution is not practical here. Developers would have trouble using memory buses wider than 64 bits due to the broad temperature requirements and the high level of cost pressure in the automotive market. Increasing the clock speed also has its limits, as times for a single bit are less than 600ps while the signal delay is twice or three times longer on the circuit board. This situation is improved by the use of a multi-step cache concept that avoids unnecessary memory access from the outset.

Figure 4: R-Car generation 2—A scalable family.

The R-Car family includes an integrated, scalable cache solution. Each CPU has the usual combination of data and command caches, and the A15 and A7 cores each have their own L2 cache. This means that most data and command access can be kept out of the external memory. Without this type of caching, the eight cores would generate 60GB/s memory transfers, while with it this value can be reduced to a much more reasonable 3GB/s. The R-Car H2 uses an additional system cache that is available to all hardware accelerators, including the image recognition processor and the audio DSPs. The 3D graphics accelerator uses tile-based rendering, which uses on-chip memory to render graphics and minimises access to external memory. The external DDR3 SDRAM memory interfaces can be scaled from 16bit to 64bit providing memory bandwidth between 2.7 GB/s and 12.8 GB/s, depending on the performance required and the available power dissipation budget (figure 3).

With all these measures, Renesas has succeeded in developing a scalable application processor family (figure 4) that enables customers to benefit from the performance of the fastest mobile processors available devices designed to mitigate the challenges in the automotive field. It is now possible to achieve power consumption of under 5W for typical navigation applications. With the integration of image recognition processors and several video interfaces, the R-Car is well equipped for the upcoming driver assistance systems. The R-Car compatible product range allows developers to select the suitable product for their application and simply upgrade if the application requires it.

About the author
Peter Fiedler is Manager for Automotive Information Systems in the MCU Marketing & Engineering division of the Automotive Business Group, Renesas Electronics Europe.

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