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Exploring i.MX 6 audio clock configuration options

Posted: 22 Jul 2014     Print Version  Bookmark and Share

Keywords:clock jitter  i.MX 6  SoC  Freescale SABRE  processor 

This application note enables users to design and route audio clocking signals. Through several use cases, this document illustrates clock jitter values of the i.MX 6 system-on-chip (SoC) family, measured on the Freescale SABRE AI and SABRE SD development platforms.

The reader will be enabled to choose the appropriate audio clocking scheme for the i.MX 6 SoC and become familiar with the expected jitter values in different scenarios.

The i.MX 6 processor family has a dedicated Audio PLL (PLL4), which, along with the Audio IP (Intellectual Property) module, generates signals for a wide range of audio peripherals. The PLL4 can be configured to generate a reference clock in the 650 MHz to 1.3 GHz range. Operating the audio PLL module in this range conditions it to provide common clock signals (such as a bit clock, word clock, and so on) which are required for external audio peripherals. This makes the i.MX6 family is touted as an excellent choice for audio applications ranging from the low-cost to high-definition.

View the PDF document for more information.

Originally published by Freescale Semiconductor Inc. at as "i.MX 6 Audio Clock Configuration Options".

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