Emulation sol'ns boost verification of memory products

Mentor Graphics Corp. has developed emulation solutions to fast-track the verification of high-performance memory products that use the latest-generation standards: Hybrid Memory Cube (HMC), LPDDR4, and eMMC 5.0.

Using these emulation solutions with the Veloce emulation platform, designers can test new devices integrated on their System-on-Chip (SoC) designs, and develop and stress-test their software and hardware with billions of verification cycles before silicon is available.

SoC designers require higher memory bandwidth and performance in response to the challenges created with products such as mobile multimedia devices and new networking infrastructure. To address this requirement, Mentor has created models for emerging memory standards that can be accelerated on the Veloce2 emulator. The combined solution delivers functionality and performance to meet critical system-level verification needs.

HMC is a 3D-DRAM architecture that can deliver memory bandwidths in excess of 100Gbit/s, or 15 times that of DDR3 memories, while consuming 70 per cent less energy/bit than DDR3. HMC is increasingly used to meet the 100G and higher networking application requirements, and is also targeted for higher GPU and CPU bandwidth needs.

The LPDDR4 and eMMC 5.0 memories are complementary technologies used in ultra-mobile products, such as tablets, superphones, and ultrabooks where LPDDR4 is used for DRAM, and eMMC 5.0 is used for mass storage. High bandwidth and performance, low power and cost, and a small form factor are key characteristics that make these memory standards attractive for today's SoC designers.

All three memory models can now be used by verification engineers, in conjunction with the rest of their SoC design running in the Veloce emulator, in a plug-and-play way that eases their adoption in an accelerated verification environment. In addition, each memory device model is compatible with the Questa functional verification platform to allow an easy transition from simulation to emulation.

The new memory device models can be used for traditional in-circuit emulation (ICE), virtual lab emulation, and high-performance, transaction-based acceleration. When combined with the Veloce2 emulator, these memory solutions deliver high-performance and easy-to-use IP and system-level verification for verifying SoCs containing HMC, LPDDR4, or eMMC 5.0 devices, without compromising delivery schedules.