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Xilinx Vertex 7 dev board supports 16K TCP & UDP accelerators

Posted: 04 Jul 2014     Print Version  Bookmark and Share

Keywords:Intilop  Xilinx Vertex 7  development board  TCP  UDP 

Intilop Inc. has uncloaked a Xilinx Vertex 7 based development platform (INT_VC707) with pre-ported and tested 10G TCP & UDP Accelerators (TCP & UDP Full Offload Engines) that implement from 2-16 thousand simultaneous TCP & UDP connections, unlimited continuous connections and bandwidth of more than 1.1GB/s per port regardless of number of simultaneous or active TCP & UDP Sessions.

In addition, it delivers the same hyper performance with same ultra-low latency (TCP/UDP) and zero jitter, irrespective of number of active connections, stated the company.

Xilinx Vertex 7 based development platform

The FPGA platform offers an 'Out of the box' working TCP & UDP hardware stacks with unprecedented functionality, ultra small core size, performance and flexibility. The full TCP and UDP cores run without any CPU involvement. The TCP and UDP connections maintain the same high throughput and low latency/processing times regardless of number of simultaneous connections in progress. This is a vast difference compared with other leading TCP accelerators that implement partial TCP offloads and suffer major performance degradation when handling just 10-20 simultaneous TCP sessions, not to speak of thousands of simultaneous TCP connections. The unprecedented TCP throughput of more than 95 per cent for large and small size payload data transfers on a 10G network, which is 8-20x higher as compared to TCP/IP software running network traffic which is the de-facto standard.

In addition, the whole SOC subsystem containing PHY & EMAC & TOE & UOE, only takes up less than 12K slices/26K LUTs and 4MB BRAM. It also integrates a DDR-III interface. The architectural innovation allows it to automatically switch to DDR when running thousands of TCP/UDP sessions. Customers can also use the DDR-III to have maximum flexibility. They will be able to use smaller and less expensive FPGAs or ASIC technology to get all of the benefits of TCP/UDP hardware acceleration. A complete FPGA board/development kit is delivered with pretested TOE/UOE subsystem that allows customers to start using it right away. It is expected to hasten the adaption of this technology in the vast array of next generation network connected devices. This technology and platform offers many system level choices and flexibilities to customers in pretty much every vertical market who are building solutions for hyper performance networking applications.

The latency barrier of sub 100ns and throughput of more than 1GB/s per port had been set by them since their first 10G Series of TCP engines in 2011. And, now the same performance metrics are provided across all 16 thousand simultaneous TCP and UDP sessions. The highly deterministic performance, reliable and proven ultra-low latency, coupled with customisability offered by the 10G TOE & UOE is being effectively applied to gain wire-speed competitive edge by all networking equipment makers.

The TOE's patent pending architecture is highly scalable, customisable and adaptable without compromising the low latency and performance, stated the company. Intilop's product-line solutions are available in flexible FPGA/ASIC/SoC technologies that can easily accommodate diverse set of appliance maker's technical design specifications.

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