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Optimising software for power efficiency (Part 3)

Posted: 04 Jul 2014     Print Version  Bookmark and Share

Keywords:embedded system  DDR  SRAM  memory accesses  DSPs 

Memory-related functionality can be quite power-hungry as clocks in an embedded system design have to be activated not only in the core components, but also in buses and memory cells. Luckily though, memory access and data paths can also be optimised to reduce power.

This third in a series of articles covers methods to optimise power consumption with regard to access to DDR and SRAM memories by utilising knowledge of the hardware design of these memory types. Then we will cover ways to take advantage of other specific memory set-ups at the SoC level.

Common practice is to optimise memory in order to maximise the locality of critical or heavily used data and code by placing as much in cache as possible. Cache misses incur not only core stall penalties, but also power penalties as more bus activity is needed, and higher-level memories (internal device SRAM, or external device DDR) are activated and consume power. As a rule, access to higher-level memory such as DDR is not as common as internal memory accesses, so high-level memory accesses are easier to plan, and thus optimise.

DDR overview
The highest level of memory we will discuss here is external DDR memory. To optimise DDR accesses in software, first we need to understand the hardware that the memory consists of. DDR SDRAM, as the DDR (dual data rate) name implies, takes advantage of both edges of the DDR clock source in order to send data, thus doubling the effective data rate at which data reads and writes may occur. DDR provides a number of different types of features which may affect total power utilisation, such as EDC (error detection), ECC (error correction), different types of bursting, programmable data refresh rates, programmable memory configuration allowing physical bank interleaving, page management across multiple chip selects, and DDR-specific sleep modes.

Key DDR vocabulary to be discussed
Chip Select (also known as Physical Bank): selects a set of memory chips (specified as a "rank") connected to the memory controller for accesses.

Rank: specifies a set of chips on a DIMM to be accessed at once. A Double Rank DIMM, for example, would have two sets of chips—differentiated by chip select. When accessed together, each rank allows for a data access width of 64 bits (or 72 with ECC).

Rows are address bits enabling access to a set of data, known as a "page"—so row and page may be used interchangeably.

Logical banks, like row bits, enable access to a certain segment of memory. By standard practice, the row bits are the MSB address bits of DDR, followed by the bits to select a logical bank, finally followed by column bits.

Column bits are the bits used to select and access a specific address for reading or writing.

On a typical embedded processor, like a DSP, the DSPs' DDR SDRAM controller is connected to either discrete memory chips or a DIMM (dual inline memory module), which contains multiple memory components (chips). Each discrete component/chip contains multiple logical banks, rows, and columns which provide access for reads and writes to memory. The basic idea of how a discrete DDR3 memory chip's layout is shown in figure 9.

Figure 9: Basic drawing of a discrete DDR3 memory chip's rows/columns.

Standard DDR3 discrete chips are commonly made up of eight logical banks, which provide addressability as shown above. These banks are essentially tables of rows and columns. The action to select a row effectively opens that row (page) for the logical bank being addressed. So different rows can be simultaneously open in different logical banks, as illustrated by the active or open rows highlighted in the picture. A column selection gives access to a portion of the row in the appropriate bank.

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