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IP portfolio optimises 28HPC for IoT SoC designs

Posted: 26 Jun 2014     Print Version  Bookmark and Share

Keywords:IP  IoT  DesignWare  28nm  HPC 

The growing IoT market landscape is having every firm come up with a solution to accommodate the low-power demands of smaller devices. Synopsys CEO Dr. Aart de Geus in his keynote speech at the Synopsys User Group (SNUG) conference in India today, in a way, described this as a dynamic activity in the industry with which designers have to constantly keep pace.

The good news is that everyone's up for the challenge, said de Geus.

Recently, Synopsys released DesignWare portfolio for TSMC's 28nm high-performance compact (HPC) process including interface, analogue, embedded memory and logic library IP. The portfolio promises to deliver high performance with low leakage and active power in a compact footprint, giving designers the ability to optimise their mobile and IoT SoC designs for energy efficiency, area and speed.

Compared with the 28LP process, the 28HPC reduces power consumption by up to 30 per cent and area by up to 10 per cent, said Suk Lee, TSMC senior director, design infrastructure marketing division. Overall, the performance is improved by up to 20 per cent.

With its production-ready DesignWare IP, Synopsys intends to reduce risks for designers who want to take advantage of the lower power consumption, area reduction and performance improvements that the 28HPC process offers.

The company's interface IP solution covers support for the most widely used interfaces such as PCI Express, USB, DDR, SATA, HDMI, MIPI, and Ethernet. The analogue IP portfolio, meanwhile, is optimised to serve as analogue interfaces to the SoC, deploying high-performance ADCs, DACs, audio analogue codecs and complete analogue front-ends (AFE) for communications and analogue video.

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Overview of the DesignWare IP portfolio. Source: Synopsys

The DesignWare double packages of embedded memories and logic libraries include memory compilers, ROMs, standard cells, power optimisation kits and optional overdrive/low voltage PVTs that enable designers to achieve the maximum performance with the lowest possible power consumption for their specific application.

An HPC design kit is also available for the 28HPC. It contains a suite of high-speed and high-density memory instances and logic cells designed to enable SoC designers to optimise their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three.

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The design kit contains a selection of high speed and high density embedded memories and standard cells that enable optimised implementations of all processors on an SoC. Source: Synopsys





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