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Qualcomm underscores need for monolithic 3D ICs

Posted: 19 Jun 2014     Print Version  Bookmark and Share

Keywords:Qualcomm  monolithic 3D IC  Moore's Law  EDA  interconnect 

According to Karim Arabi, Qualcomm's VP of engineering, the company "is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase. He also emphasised that 3D and EDA need to make up for Moore's Law.

This was the third time in the past year that Qualcomm executives have made such a call at major industry conferences. At IEDM 2013, Geoffrey Yeap, Qualcomm's VP of technology, stated in his invited talk: "As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore's Law." Yeap provided the following chart for the growing gap between transistor delay and interconnect delay:

The growing gap between transistor delay and interconnect delay

BEOL performance/area/cost scaling is the foremost issue for the 10nm and 7nm technology nodes.

Earlier that year, Robert Gilmore, Qualcomm's VP of engineering, in his invited talk at VLSI 2013 (Kyoto, Japan), used almost the same words and provided the following illustration (note the wafer is face-down):

Typical layer structure of a monolithic 3D-IC

Typical layer structure of a monolithic 3D-IC

Clearly, there seems to be a concentrated effort by Qualcomm to promote the development and adoption of monolithic 3D. In fact, Qualcomm has done more than just talking, it has been investing in monolithic 3D development tools with institutions such as Georgia Tech. Qualcomm has also been filing patents in this area, and recently announced an agreement to work with CEA-Leti.

It would seem that the number one motivation behind these efforts is Qualcomm's concern about future cost reductions. Early in 2012, Jim Clifford, Qualcomm's VP and GM (at that time), in his plenary talk at the SPIE conference titled A Mobile Wireless Phenomenon: A Continued Need for Advanced Lithography, made it very clear with his second slide. At that time there were already some concerns with the rollout schedule for extreme ultraviolet lithography (EUV). Jim called on the conference attendees to make sure to solve the escalation of advanced lithography cost, which was already dominating more than 50 per cent of the overall advanced device cost. Jim presented the following curve showing the historical 29 per cent cost reduction per year and the looming problem with the production cost beyond 28nm:

Ongoing chip cost reduction is a must for new technology nodes

Ongoing chip cost reduction is a must for new technology nodes. (Source: ITRS)

Jim continued: "If the next node doesn't cost less than the last node, we got a problem because I don't think the demand will be there." Well, it is now clear that EUV is not ready and that dimensional scaling below 28nm will require double and triple lithography with its associated additional costs.

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