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Optimising software for power efficiency (Part 2)

Posted: 23 Jun 2014     Print Version  Bookmark and Share

Keywords:Data flow  Hardware optimisation  DSP  Power gating  MSC815x 

Data flow optimisation focuses on working to reduce the power cost of utilising different memories, buses, and peripherals where data can be stored or transmitted by taking advantage of relevant features and concepts. Algorithmic optimisation refers to making changes in code to affect how the cores process data, such as how instructions or loops are handled.

Hardware optimisation, as discussed here, focuses more on how to optimise clock control and power features provided in the microprocessor or peripheral circuits.

Hardware support
Low power modes. DSP applications normally work on tasks in packets, frames, or chunks. For example, in a media player, frames of video data may come in at 60 frames per second to be decoded, while the actual decoding work may take the processor orders of magnitude less than 1/60th of a second, giving us a chance to utilise sleep modes, shut down peripherals, and organise memory, all to reduce power consumption and maximise efficiency.

We must also keep in mind that the power-consumption profile varies based on application. For instance, two differing hand-held devices, an MP3 player and a cellular phone, will have two very different power profiles.

The cellular phone spends most of its time in an idle state, and when in a call is still not working at full capacity during the entire call duration as speech will commonly contain pauses which are long in terms of the processor's clock cycles.

For both of these power profiles, software-enabled low-power modes (modes/features/ controls) are used to save power, and the question for the programmer is how to use them efficiently. A quick note to the reader: different device documents may refer to features discussed in this section such as gating and scaling in various ways, such as low-power modes, power saving modes, power controls, etc. The most common modes available consist of power gating, clock gating, voltage scaling, and clock scaling.

Power gating. This uses a current switch to cut off a circuit from its power supply rails during standby mode, to eliminate static leakage when the circuit is not in use. Using power gating leads to a loss of state and data for a circuit, meaning that using this requires storing necessary context/state data in active memory. As embedded processors are moving more and more towards being full SoC solutions with many peripherals, some peripherals may be unnecessary for certain applications. Power gating may be available to completely shut off such unused peripherals in a system, and the power savings attained from power gating depend on the specific peripheral on the specific device in question.

It is important to note that in some cases, documentation will refer to powering down a peripheral via clock gating, which is different from power gating. It may be possible to gate a peripheral by connecting the power supply of a certain block to ground, depending on device requirements and interdependence on a power supply line. This is possible in software in certain situations, such as when board/system-level power is controlled by an on-board IC, which can be programmed and updated via an I2C bus interface. As an example, the MSC8156 DSP (figure 5) has this option for the MAPLE DSP base band accelerator peripheral and a portion of M3 memory.

Figure 5: 8156 six-core DSP processor.

Clock gating. As the name implies, this shuts down clocks to a circuit or portion of a clock tree in a device. As dynamic power is consumed during state change triggered by clock toggling (as we discussed in the introductory portion of this chapter), clock gating enables the programmer to cut dynamic power through the use of a single (or a few) instructions. Clocking of a processor core like a DSP is generally separated into trees stemming from a main clock PLL into various clock domains as required by design for core, memories, and peripherals, and DSPs generally enable levels of clock gating in order to customise a power-saving solution.

Examples of low-power modes
The Freescale MSC815x. These DSPs provide various levels of clock gating in the core sub-system and peripheral areas. Gating clocks to a core may be done in the form of STOP and WAIT instructions. STOP mode gates clocks to the DSP core and the entire core sub-system (L1 and L2 caches, M2 memory, memory management, debug and profile unit) aside from internal logic used for waking from the STOP state.

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