Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > FPGAs/PLDs

Quick start guide for Petaluma ZedBoard

Posted: 25 Jun 2014     Print Version  Bookmark and Share

Keywords:Petaluma  FPGA  Xilinx  PlanAheadProject  Zynq 

This application note provides a high-level overview of the steps required to quickly get the Petaluma design running by downloading and running the FPGA project. Detailed instructions for each step are provided in the document. The Petaluma (MAXREFDES30#) sub-system reference design will be referred to as Petaluma throughout the document.

The top level of the hardware design is a Xilinx PlanAheadProject for Xilinx PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides FPGA/board net connectivity, and instantiates the wrapper that carries both the Zynq Processing System and AXI_MAX11046 custom IP core that interface to the FMC connector. This is supplied as a Xilinx software development kit (SDK) project that includes a demonstration software application to evaluate the Petaluma sub-system reference design. The lower level c-code driver routines are portable to the user's own software project.

View the PDF document for more information.

Originally published by Maxim Integrated Products Inc. at as "Petaluma (MAXREFDES30#) ZedBoard Quick Start Guide".

Comment on "Quick start guide for Petaluma ZedBo..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top