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EE Times-India > EDA/IP

Online tools aim to ease SoC design

Posted: 12 Jun 2014     Print Version  Bookmark and Share

Keywords:eSilicon  SoC design  Internet  online tool  IDM 

According to the founder, president and CEO of eSilicon, SoC designers haven't entirely utilised the full potential of the Internet when it comes to design. However, Jack Harding said the emergence of design service companies such as eSilicon has eliminated many of the hassles of managing design and manufacturing in the backend for many integrated device manufacturers (IDMs) and fabless chip companies.

As Step 2 of the company's business development, whose original mission was to automate the entire chip development process, eSilicon rolled out two online tools with which designers can explore design and delivery options. One is a tool called IP MarketPlace, through which users can configure eSilicon-designed, compilable SRAM IP blocks. SoC designers can use it to browse memory configurations to define the best power, performance or area fit for a particular SoC design.

Another is a GDSII portal. GDSII is a database file format for data exchange in ICs. The portal enables SoC designers to explore various options for taping out to foundries' processes. They can compare the cost involved in different nodes, packaging, testing, and delivery, generating a "price-guaranteed cost estimate" for designing a new chip, stated Harding.

True to the online world, SoC designers will now be able to make such front-end design decisions online "untouched by human hands" without even talking to a single person (for price negotiations) or making a financial commitment.

In essence, these Web-based tools developed for SoC designers are equivalent to what Kayak is to consumers when travel shopping.

Harding stated, "Our industry built the Internet, and continues to develop solutions that enable cloud services. But I don't think we use the Internet enough."

Harding added that his company's online tools will accelerate the adoption of Internet commerce for SoC designers.

SoC designers of big semiconductors such as Qualcomm, Broadcom and Marvell might remain skeptical of such tools, however. When asked about eSilicon's GDSII portal, Philip Poulidis, VP of the Internet of Things business unit at Marvell, said he's intrigued. But he added that these tools don't fit companies such as Marvell, whose well negotiated deals with foundries are set in place.

Other industry observers note that for tools such as these to take off, more design starts are needed, which explains why eSilicon is hungrily watching growth rates in the IoT market.

Harding suspects that small to midsized fabless companies planning to get into the IoT chip market might push the adoption of online tools. "IoT SoCs aren't particularly complicated. But those SoCs will be greatly affected by the cost of IP, process nodes, packaging and testing."

When there are thousands of possible permutations in design, the hitch is that chip designers often don't know the actual cost of a new SoC until the design is done, noted Harding, who contends that one needs such information up front. "You can't afford to make decisions out of personal preferences."

Starting new online businesses, especially in new fields, takes a leap of faith. When asked how eSilicon actually makes money by offering online tools for free, Harding said, "I have no idea. And that's what I told the board of our company." However, one point is absolutely clear: "I didn't want to be the guy who didn't embrace the Internet."

When SoC design costs too much, innovation shuts down, Harding indicated. The industry needs tools that can save millions of dollars. "Anyone who wouldn't use tools for free is a fool."

- Junko Yoshida
  EE Times

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