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Suite allows optimisation of complex electronic systems

Posted: 11 Jun 2014     Print Version  Bookmark and Share

Keywords:Mentor Graphics  electronic system  suite  board design 

Mentor Graphics Corp. has introduced the Xpedition Path Finder product suite that affords designers with the ability to assemble and optimise complex electronic systems, promising improved design, increased chip performance and cost efficiency. The latest addition to the Mentor Graphics Xpedition platform, supports a methodology that leverages layout data from the IC and board design teams to guide and automate IC package selection and optimisation, noted the company.

The Xpedition Path Finder suite provides a single environment that gives cross-domain design teams the ability to model every device/interface to the level of detail and accuracy they require. IC layout design data can be represented as a virtual die model (VDM), containing all of the IC-level detail specific to the co-design and optimisation process. Board design data can be modelled as individual interfaces or as complete designs. Packages can be built based on industry-leading pin array generation and manipulation capabilities, existing devices, and industry-standard formats. Cross-domain design teams can now make smart planning and optimization decisions related to cost and performance of their IC package in context of the complete system.

The Xpedition Path Finder suite addresses the increasing design complexity of SoCs and multi-die packaging growth by providing the industry's first path-finding methodology that automates the planning, optimisation and connectivity from a chip through multiple packaging variables, while targeting multiple and different PCB platforms, detailed Mentor.

Using the multi-mode connectivity environment, designers can capture and manage connectivity based on their preference; table-based, graphical schematics or automated. Cross-domain pin mapping and net combining can easily be managed in all modes of connectivity capture. In addition, users can perform rules-based pin/ball-out studies from their respective domains, by signal, bus or interface, visualising the impact across the complete system in real time. Path Finder also streamlines and automates the library development process, reducing a several day task down to a few minutes.

Xpedition Path Finder

The Xpedition Path Finder suite is comprised of a multi-mode connectivity engine and optimisation engine/editor, leveraging a physical layout tool with industry-leading routing technology. It has a correct-by-construction layout environment that enables designers to boost performance and manufacturability on the densest designs populated by high-pin-count flip-chip BGAs. The core Xpedition layout tool provides: unique BGA breakout and escape algorithms coupled with support for complex microvia structures; shape-based, any-angle routing; plane areas that dynamically fill around traces and vias during editing; patented technology enabling efficient, concurrent design by large teams; and integrated RF circuit design and optimisation.

The suite features a rule-based ball-out assignment, including an optimisation engine/editor for planning by bank, byte, reference voltage, clock domain, etc., an intelligent way to show a ball map: simply create, import, and export. It also flaunts a single tool for multi-mode physical design (PCB, MCM, SiP, RF, Hybrid and BGA designs) that reduces design time orders of magnitude compared to other available products, using Microsoft-based Component Object Model (COM) automation for robust extension and customisation capabilities.

The Xpedition Path Finder suite boasts a streamlined and fully automated library development; Virtual Die Model (VDM) to accurately capture IC layout (floor planning) design intent, facilitating WYSIWYG IC and package co-optimisation; and tight integration with 2D and 3D electro-magnetic (EM) and computational fluid dynamics (CFD) thermal analysis engines.

The Xpedition Path Finder suite is available.

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