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The importance of RTL signoff

Posted: 03 Jun 2014     Print Version  Bookmark and Share

Keywords:RTL signoff  Functional coverage  Clock domain crossings  Timing constraints  Power consumption 

RTL signoff gathered momentum as an established concept in 2013. It is unclear though if a commonly-accepted definition of RTL signoff actually exists.

I believe that it is a comprehensive series of well-defined MUST-pass requirements that your RTL needs to attain before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL signoff requirements, you will need the means to measure them against your design as well as reports to ensure compliance.

Some examples of RTL signoff MUST-pass requirements include:
 • Functional coverage (including high quality assertions)
 • Clock domain crossings (static and dynamic verification)
 • Timing constraints (including false and multi-cycle paths)
 • Power consumption (and meeting the power budget)
 • Power intent (CPF / UPF correct?)
 • Testability (stuck-at and at-speed coverage OK?)
 • Routability (congestion OK; area and timing OK?)

There are other strains of thought, RE: what constitutes reliable RTL signoff. Running SoC designs through rigorous checks of a few to several critical functions certainly saves time and focuses RTL signoff resources on more critical areas where your SoC will most likely have problems.

Figure 1: Traditional signoff.

But that's a lot like saying a car doesn't need a chassis and four wheels to roll ... that you only need three wheels and the car more than likely will roll fine. It's a decent bet ... but I also wager that a lot of SoC designers would prefer to have the chassis and four wheels approach and be absolutely sure their SoC has signed off at RTL.

What has changed in today's SoC design to require this RTL signoff mandate? There's been an explosion in design complexity resulting from hyper integration of multiple functions on a single chip. Compounding this issue, increasing reliance on externally sourced semiconductor Intellectual Property (IP) content, both from 3rd party suppliers and from other design groups within the same company, impedes the quality assurance process.

In many cases, the SoC replaces an entire printed circuit board (PCB) in a previous generation device, or the entire device itself. What does this mean to the SoC? A surge of functionality (computing, audio, video, wireless, gaming, external interfaces, memory interfaces, power management, etc.) is crammed into a single chip the size of your thumbnail.

We are beginning to see SoC designs with more than a billion gates. It is a staggering task to ensure that all SoC functions work seamlessly, that the device can be manufactured reliably, is cost effective, has hours of battery life, and responds instantly to your every command. Although we expect no less from our electronic devices, meeting all these requirements can be quite overwhelming.

The explosion in design complexity is further compounded by very short market windows and shrinking product cycles – sometimes windows of only 3-6 months – turning a healthy profit margin into a significant loss.

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