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Synopsys touts PCI Express 4.0 IP solution

Posted: 26 May 2014     Print Version  Bookmark and Share

Keywords:Synopsys  PCI Express 4.0  SoC  SSD  enterprise computing 

Synopsys Inc. has rolled out what it claims to be the first complete PCI Express 4.0 IP solution, consisting of DesignWare PHY, controllers and verification IP (VIP) aimed at enterprise computing applications such as servers, networking, storage systems and solid state drives (SSDs). The PCI Express 4.0 specification, the next generation of the PCI Express I/O standard, doubles throughput to 16GT/s and is at a preliminary revision 0.3 within the PCI Special Interest Group (PCI-SIG).

The DesignWare IP for PCI Express 4.0 is said to enable easy SoC integration of 16GT/s performance and the power-saving features defined in the PCI Express 4.0 specification. The DesignWare PHY IP for PCI Express 4.0 will support full-featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5, 5, 8 or 16GT/s, or to aggregate the PHY macro up to 16 lanes. For increased signal integrity at high-speed data rates across legacy channels, the PHY analog front-end will include 5-tap DFE, continuous time linear equalisation (CTLE) and feed forward equalisation (FFE) with advanced algorithms for link initialisation and adaptation. As power reduction is a key requirement in many markets, the DesignWare PHY IP will reduce both active and standby power consumption through advanced techniques including L1 sub-states, added Synopsys. Support for Separate Refclk Independent SSC (SRIS) will allow the use of cables to enable a new class of PCI Express applications outside of the system.

The low-power, low-latency DesignWare controller IP is backward compatible with the endpoint, dual mode and root complex port types, with support from embedded DMA and SR-IOV. ARM AMBA 4 AXI, AMBA 3 AXI and AMBA AHB and native interfaces are alsoavailable in said controller IP. It also supports multiple lanes (x1 to x16) and multiple data path widths, minimising gate counts and reducing design risk.

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