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Cadence DDR4 PHY IP developed on 16nm FinFET process

Posted: 21 May 2014     Print Version  Bookmark and Share

Keywords:Cadence Design Systems  FinFET  DRAM  DDR4 PHY IP  SoC 

Cadence Design Systems Inc. has revealed a DDR4 PHY IP built on TSMC's 16nm FinFET process. According to the company, the combination of 16nm technology and its innovative architecture helps customers realise the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mb/s, as compared to the current maximum of 2133Mb/s for both DDR3 and DDR4 technologies.

This technology enables server, network switching, storage fabric and other SoCs requiring high-memory bandwidth to design-in Cadence DDR4 PHY IP now and to exploit higher speed DRAMs when they become available.

The Cadence DDR4 PHY IP supports an unbuffered dual in-line memory module (UDIMM)/registered dual in-line memory module (RDIMM) with reliability, availability and serviceability (RAS) features such as cyclic redundancy check (CRC) and data bus inversion (DBI). The DDR4 PHY IP implements architectural innovations such as 4X clocking to minimise duty cycle distortion, multi-band power isolation for increased noise immunity and I/O with slew rate control. The Cadence DDR4 PHY IP together with Cadence DDR4 controller are verified in silicon from TSMC's 16nm FinFET process.

"The demand for 16nm FinFET-based designs continues to grow and is driving the market need for a complementary DDR4 IP offering," said Suk Lee, TSMC senior director, design infrastructure marketing division. "Because we have worked very early and closely with Cadence on this technology, our customers can review the design's silicon results to feel confident about turning to Cadence for comprehensive 16nm support from tools to IP."

"Many of our customers are concerned that their next-generation designs might not reach their performance goals because of the bottleneck in memory systems," stated Martin Lund, Cadence's SVP and GM of the IP Group. "By using Cadence DDR4 IP, we believe our customers can have more confidence that their products will work with future DRAMs designed for higher speeds."

DDR4 PHY IP is silicon-tested and available now.





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