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Advances in MCUs and test equipment

Posted: 20 May 2014     Print Version  Bookmark and Share

Keywords:microcontrollers  MCUs  parallel testing  multi-site efficiency  Advantest 

By just changing the MSE to 99.9%, which is quite possible depending on the chip, you can raise the throughput to 11,174 units per hour, an increase of 57%. If you then increase the number of parallel tested chips to 64, you can achieve a throughput of 21,675 units. That's 200% more throughput. In other words, you need two fewer test cells.

The first immediate challenge with parallel test is to make sure that you have enough resources for the tester to perform at its full ability. Through a classical approach this is achieved by installing more plug-in modules for the tester, with the risk of space running out. This means that you have to compromise not only parallel test, but also serial test on analogue interfaces. Serial testing raises the test time dramatically, with MSE and throughput dropping accordingly.

MCUs contain more and more System on a Chip (SOC) components which results in them being tested on SOC testers. Technically speaking, this is the right approach. From an economic point of view, however, the investment costs have to be taken into consideration as these can very quickly spiral out of control. SOC testers also don't have unlimited space to accommodate the various plug-in modules needed for different test requirements.

Figure 1: With increasing parallelism, the throughput (XPUT) in units per hour (UPH) changes dramatically with minor adjustment to the MSE.

The Advantest V93000 is a tester that was initially deployed to test complex SOCs, but has since evolved into an MCU tester. With its universal pin function, one single channel offers all the functions necessary to test an MCU: voltage supply, digital test and analogue test.

Each V93000 Smart Scale generation channel on the PS1600 card covers voltage levels ranging from 2.0V to 6.5V. This means that not only can it supply voltage, but it can measure it as well. One important requirement for MCU testing is DC measurement accuracy down to the 10nA range.

The ADC on the PS1600 board can be utilised as a digitizer and allows for static tests of 12 to 14bit DACs. This is an 18bit digitizer with a maximum sample rate of ~ 50ksps and is perfectly adequate for linearity measurements and some audio measurements.

1.6Gbit/s is the maximum digital data throughput of the PS1600 card which is more than sufficient for most MCUs. When this signal is sent through a filter it produces an AWG with a sample rate of 100 Msps. This feature covers both the static and dynamic testing of 12 to 14bit ADCs. The signal distribution matrix on the PS1600 card allows this signal to be routed to other channels on the board and provides a fan-out in the tester. The PPMU integrated in every channel on the card can be used to run static and dynamic tests on 10 to 12bit ADCs. This allows for a sample rate of 200 ksps.

Figure 2: The Swiss Army Knife of MCU testing: With a throughput of 1.6 Gpbs and the capability to measure and power the DUT, the PS1600 handles most requirements.

The RF transmitter in a tyre pressure sensor, for example, can be tested by utilising the high bandwidth of the receiver on the PS1600 card and setting the oversampling to 1.6Gbit/s.

All of these functions in a single channel on the PS1600 card are pattern-controlled, which means that they can be switched on and off without using relays on the DUT board. Configurable MCUs with I/Os are capable of taking over different tasks and can be tested much more elegantly, quickly and cheaply.

The V93000 test platform from Advantest offers a range of scalable test modules that can be plugged in the tester. Should the MCU requirement be somewhat higher, it can be easily retrofitted.

About the author
Georg Michanickl is Market Development Manager MCU Market at Advantest. Previously he held positions as Market Development Manager for Korea, Business and Market Development Manager for high speed memory solutions, Market Segment Lead for computation market and Business Development Manager for US computation key accounts and European accounts at Agilent/Verigy. Prior to joining Agilent, Georg was a Product Manager for computer peripherals at Wacom and Project Coordinator for Ove Arup Consulting Engineers. He has a master of science from the University of Birmingham, England and an engineering degree from the University of Applied Sciences of Aalen, Germany.

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